Semiconductor-on-insulator chip incorporating...

Details Semiconductor-on-insulator chip incorporating... Semiconductor-on-insulator chip incorporating...

2007-09-11

2007-09-11

Richards, N. Drew (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S164000

Reexamination Certificate

active

10999564

ABSTRACT:
In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

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