Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-27
2003-12-09
Le, Dung A (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S509000, C438S143000, C438S151000, C438S406000
Reexamination Certificate
active
06660606
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an annealing method for an SOI substrate having a semiconductor layer such as a silicon layer formed on an insulator, in which the number of defects (HF defects) in an SOI layer (the semiconductor layer on the insulator) and, more specifically, the number of HF defects which increase as an SOI layer becomes thin is reduced by annealing the SOI substrate in a reducing gas atmosphere, and an SOI substrate using the annealing method.
BACKGROUND OF THE INVENTION
Sato et al. has reported a technique of annealing an SOI (Semiconductor On Insulator) wafer in a reducing atmosphere, in which, e.g., annealing in hydrogen gas at 1,000° C. yields so high planarity that the roughness on an SOI layer surface is 2 nm or less (Japanese Patent Laid-Open No. 05-217821 and U.S. Pat. No. 5,371,037).
This technique will be described with reference to
FIGS. 6 and 7
. An example using a vertical annealing furnace is shown in FIG.
6
.
Referring to
FIG. 6
, reference numeral
101
denotes a furnace tube serving as a reactor. An atmospheric gas is supplied from a supply pipe
102
arranged at the upper portion and exhausted from an exhaust pipe
103
at the lower portion. Reference numeral
104
denotes a heater; and
105
, a boat which is made of silicon carbide set on a heat barrier
107
arranged on a furnace lid
106
and holds a plurality of SOI substrates
108
. The boat
105
is formed from silicon carbide manufactured by sintering. The boat
105
may have a coating of chemically synthesized silicon carbide that is synthesized by chemical vapor phase deposition on a surface of silicon carbide manufactured by sintering.
Annealing is performed in accordance with the following procedure. The furnace lid
106
is moved downward in advance. In this state, the SOI wafers
108
are set in the boat
105
. The furnace lid
106
is moved to the position shown in
FIG. 6
to place the SOI wafers
108
in the process chamber and close the opening portion of the furnace tube
101
. The furnace lid
106
is operated by an elevating mechanism (not shown). The interior of the process chamber is replaced with a hydrogen gas atmosphere by supplying hydrogen gas from the supply pipe
102
into the furnace tube
101
.
The flow of the atmospheric gas in the annealing furnace will be described with reference to FIG.
7
. Referring to
FIG. 7
, reference numeral
101
denotes a furnace tube;
105
, a boat made of silicon carbide; and
108
, SOI substrates, as in FIG.
6
. Reference numerals
114
and
115
denote atmospheric gas flows.
The speed of the atmospheric gas flow
115
near an SOI substrate surface during annealing can be substantially set to zero, i.e., the flow can be eliminated by equalizing intervals
116
and
117
between the boat
105
and the furnace tube
101
.
The speed of the atmospheric gas flow
114
means the speed of a gas that passes through a region excluding the sectional area of the SOI substrate
108
from the sectional area of the furnace tube
101
.
Next, the interior of the process chamber is heated to a predetermined processing temperature by the heater
104
, and annealing is performed. After the elapse of a predetermined time, the temperature of the heater
104
is reduced, and then, nitrogen gas is supplied into the process chamber to replace the atmosphere. The furnace lid
106
is moved downward, and the SOI substrates
108
are unloaded. The processing temperature and time are determined in accordance with a desired annealing effect.
Another technique has been proposed in which an SOI substrate formed by bonding wafers manufactured by the CZ method (Czochralski method) is annealed in a reducing atmosphere using a rapid heating/cooling apparatus (rapid thermal annealer; to be referred to as an RTA apparatus hereinafter), thereby reducing COPs (crystal originated particles; defects observed in a silicon wafer formed by the CZ method) on an SOI layer surface (Japanese Patent Laid-Open No. 11-145020).
In addition, a technique has been proposed in which an SOI substrate formed by a method called a hydrogen ion implantation peeling method, in which a wafer with hydrogen ions implanted is bonded to another silicon wafer and then peeled to form an SOI substrate, and is annealed in a reducing atmosphere using an RTA apparatus, thereby removing the damaged layer or surface roughness of an SOI layer while maintaining the film thickness uniformity of the SOI layer (Japanese Patent Laid-Open Nos. 11-307472 and 12-124092).
One of the factors that decrease the yield of devices manufactured using SOI wafers is defects in a single-crystal Si layer (SOI layer).
Defects in an SOI layer include HF defects that are detected by dipping an SOI wafer in a concentrated HF solution (49%) at room temperature. HF defects considerably affect the electrical characteristic of a device.
HF defects are caused by various factors. Sanada et al. checked causes for HF defects in SOI wafers manufactured by a method called SIMOX (Separation by Implanted Oxygen) in which an SOI wafer is formed by implanting oxygen ions, and reported that a metal silicide forms on an SOI layer by metal contamination at the time of ion implantation or annealing and molten in HF dipping to cause HF defects (D. K. Sanada, J. Lasky, H. J. Hovel, K. Petrillo, and P. Roitian, Proc. of IEEE SOI Conf., (1994) p. 111.
Aga et al. reported that HF defects in an SOI substrate manufactured by bonding CZ wafers are caused by COPs (H. Aga, M. Nakano, K. Mitani, Jpn. J. Appl. Phys., (1999) p. 2694).
Aga et al. also described in this report that the density of these HF defects abruptly rises when the SOI layer thickness becomes 200 nm or less because small COPs at the SOI/BOX interface also cause HF defects as the SOI layer becomes thinner.
A manufacturing method (epitaxial layer transfer method) called ELTRAN (registered trademark) has been proposed in which a single-crystal layer is formed on a porous layer formed on a silicon substrate surface, and the single-crystal layer is transferred to another substrate (Japanese Patent No. 2608351).
In the SOI substrate manufactured by the above method, no COPs are formed on the SOI layer because the single-crystal silicon layer is formed by epitaxial growth by CVD (Chemical Vapor Deposition).
However, HF defects are sometimes observed even in an SOI wafer manufactured by the above method, as shown in FIG.
9
.
Thinning an SOI layer is an important technical challenge in promoting the advantages of an SOI wafer, i.e., high-speed operation and low power consumption of a device.
For example, the ITRS (SIA, The International Technology Roadmap for Semiconductors (1999) p. 110) requires to reduce the thickness of an SOI layer to 30 to 200 nm until 2003 and further to 20 to 100 nm from 2004.
From this viewpoint, reducing the number of HF defects is a very important challenge not only in improving the yield of devices but also in promoting thinning an SOI layer.
SUMMARY OF THE INVENTION
Details of how the present inventors have reached the present invention will be described below.
The present inventors extensively studied HF defects in an SOI substrate having a silicon layer formed by epitaxial growth and found that the number of HF defects tends to abruptly increase when the thickness of an SOI layer becomes less than 100 nm and also that the HF defects become conspicuous when the SOI layer thickness becomes 70 nm or less as shown in FIG.
9
. This tendency that the HF defect density abruptly rises as an SOI layer becomes thinner is consistent with the above-described report by Aga et al.
First, an SOI substrate manufacturing method using the epitaxial layer transfer method will be described below in detail with reference to FIG.
8
.
As shown in
FIG. 8
, in step S
31
, a single-crystal silicon substrate
131
is prepared as the first substrate, and a porous layer
133
is formed at least on its major surface side. Porous silicon can be formed by anodizing the silicon substrate in an HF solution. The porous layer has a sponge structure in which pores wit
Ito Masataka
Miyabayashi Hiroshi
Sato Nobuhiko
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