Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-31
2002-06-11
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S304000
Reexamination Certificate
active
06403421
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device and a method of producing the same, more particularly relates to a semiconductor nonvolatile memory device having nonvolatile memory cell of floating gate type MOS transistors and a method of producing the same.
2. Description of the Related Art
In recent years, as semiconductor nonvolatile memory devices, there have been active development and commercialization of erasable programmable read-only memories (EPROM) using floating gate type MOS transistors, electrically erasable programmable read-only memories (EEPROM), flash memories, ones of EEPROMS, adopting full erasure methods, etc.
The above-mentioned flash memories include NOR type flash memories and NAND type flash memories. The former use single floating gate type MOS transistor as the memory cell of the flash memory, while the latter use a NAND cell comprised of adjoining memory cells comprised of a plurality of, for example, N number of floating gate type MOS transistors as a unit cell.
Such NAND type flash memories are slower in speed of random access compared with NOR type flash memories, but are superior in terms of degree of integration, so have been developed and commercialized in recent years as flash memories for increasing the degree of integration.
A sectional view of an example of the above floating gate type of semiconductor nonvolatile memory device is shown in
FIG. 1. A
gate insulating film (tunnel insulating film)
20
a
comprised of for example a thin film of silicon oxide is formed on an active region of a semiconductor substrate
10
isolated by an element isolation insulating film
24
a
formed by for example the LOCOS method. A floating gate
30
b
comprised of for example polycrystalline silicon is formed at an upper layer. Further, an inter-layer insulating film
25
a
comprised of for example an oxide-nitride-oxide stacked insulating film (ONO film) is formed at an upper layer thereof. At an upper layer of the inter-layer insulating film
25
a
is formed a control gate
31
of a polycide structure comprised of for example a lower control gate
31
a
of polycrystalline silicon and an upper control gate
31
b
of tungsten silicide. In the semiconductor substrate
10
, not shown source-drain diffusion layers are formed at the two sides of the control gate
31
. Due to this, a field effect transistor is comprised, having a floating gate
30
b
covered by an insulating film between the control gate
31
and the channel formation region In the semiconductor substrate
10
.
In the floating gate type semiconductor nonvolatile memory device having the above structure, the floating gate
30
b
has the function of holding the charge in the film while the gate insulating film
20
a
and the inter-layer insulating film
25
a
have the role of sealing the charge in the floating gate
30
b
. When a suitable voltage is applied to the control gate
31
, semiconductor substrate
10
, source-drain diffusion layer, etc., a Fowler-Nordheim type tunnel current (FN current) is caused, a charge is injected through a gate insulating film
20
a
from the semiconductor substrate
10
to the floating gate
30
b
, or a charge is released from the floating gate
30
b
to the semiconductor substrate
10
.
If a charge is stored in the floating gate
30
b
, a field is generated by the stored charge, therefore threshold voltage of the transistor changes. Data can be stored by this change. For example, it is possible to erase data by storing a charge in the floating gate
30
b
or to write data by releasing the charge stored in the floating gate
30
b.
The floating gate type semiconductor nonvolatile memory device of the above related art, however, has an overlap portion I as a margin for connection of the floating gate
30
b
and the element isolation insulating film
24
a.
In particular, an element isolation insulating film obtained by the LOCOS method has a bird's beak, so the element isolation width becomes greater and the isolation voltage resistance falls. This makes it difficult to reduce the cell area.
To solve the above problem, a floating gate type semiconductor nonvolatile memory device having a self-aligned shallow trench isolation (SA-STI) cell structure which forms an element isolation region by self-alignment at the end of the floating gate in the width direction has been developed (see
IEDM Tech. Dig.
1994, pp. 61 to 64). Below, an explanation will be made of a NAND type semiconductor nonvolatile memory device having an SA-STI cell structure.
FIG. 2A
is a plan view of this. A floating gate FG covered by an insulating film is formed between a control gate CG and channel formation region of the silicon semiconductor substrate at a region where an active region of the silicon semiconductor substrate isolated by a trench type element isolation insulating film TI intersects the control gate CG to form a word line. Further, source-drain diffusion regions SD are formed in the substrate at the two sides of the control gate CG. A plurality of field effect transistors having floating gates FG covered by an insulating film between the control gate CG and the channel formation region in the semiconductor substrate, that is, memory transistors MT, are connected in series to form a NAND column. A selection MOS transistor ST for selecting the NAND column is formed at the other end of the NAND column and has a drain diffusion layer connected through a bit contact BC to a not shown bit line. A not shown selection MOS transistor is also formed at the other end of the NAND column and has a source diffusion layer connected to the source line S.
An equivalent circuit diagram of the semiconductor nonvolatile memory device shown in the plan view of
FIG. 18A
is shown in FIG.
2
B. Memory transistors (MT
1
a
, MT
2
a
, MT
3
a
, . . . ) are connected in series to form a NAND column. A selection MOS transistor STa for selecting the NAND column is formed at one end of the NAND column and has a drain diffusion layer connected through the bit contact BCa to the bit line BLa. A not shown selection MOS transistor is formed at the other end of the NAND column and has a source diffusion layer connected through a sub source line Sa to a main source line S. Another NAND column comprised of a memory transistor MT
1
a
′ etc. selectable by a selection MOS transistor STa′ is also connected to the bit line BLa. On the other hand, memory transistors (MT
1
b
, MT
2
b
, MT
3
b
, . . . ) are connected in series to form a NAND column. A selection MOS transistor STb for selection of this NAND column is formed at one end of this NAND column and has a drain diffusion layer connected through the bit contact BCb to the bit line BLb. The source diffusion layer of a not shown selection MOS transistor formed at the other end of the NAND column is connected through a sub source line Sb to the main source line S.
A sectional view along the line A-A′ in
FIG. 2A
of the semiconductor nonvolatile memory device is shown in
FIG. 3A and a
sectional view along the line B-B′ is shown in FIG.
3
B. As shown in
FIG. 3A
, a gate insulating film (tunnel insulating film)
20
a
comprised of, for example, a thin film of silicon oxide is formed on an active region of the semiconductor substrate
10
isolated by a trench type element isolation insulating film
24
a.
A floating gate
30
b
comprised of for example polycrystalline silicon is formed at the upper layer. Further, an inter-layer insulating film
25
a
comprised of for example an ONO film is formed at an upper layer of this. A control gate (word line)
31
covering the upper surface of the inter-layer insulating film
25
a
and comprised of for example polycrystalline silicon is formed. Further, as shown in
FIG. 3B
, source-drain diffusion layers
13
are formed in the semiconductor substrate
10
at the two sides of a control gate
31
. Due to this, a field effect transistor having a floating gate
30
b
covered by an insulating film between the control
Ikeda Naoshi
Yamamura Ikuhiro
Yamanaka Hidetoshi
Brewster William M.
Dang Trung
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
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