Semiconductor memory with test circuit

Details Semiconductor memory with test circuit Semiconductor memory with test circuit

1999-01-22

1999-12-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365190, G11C 700

Patent

active

060026235

ABSTRACT:
A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.

REFERENCES:
patent: 5241501 (1993-08-01), Tanaka

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