Semiconductor memory with reduced peak current

Details Semiconductor memory with reduced peak current Semiconductor memory with reduced peak current

1992-04-02

1994-01-04

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365149, 365203, G11C 700

Patent

active

052766454

ABSTRACT:
A semiconductor memory has sense amplifiers coupled to complementary pairs of bit lines. A first switching element couples the sense amplifiers to a first potential, so that the sense amplifiers can bring one bit line in each pair of bit lines from a precharged state to the first potential. A second switching element couples the sense amplifiers to a shunt node. A third switching element couples the shunt node to the first potential. A capacitor capacitively couples the shunt node to a second potential different from the first potential.

REFERENCES:
patent: 4144590 (1979-03-01), Kitagawa et al.
patent: 4926383 (1990-05-01), Kertis et al.

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