Semiconductor memory device having a voltage lowering circuit of

Details Semiconductor memory device having a voltage lowering circuit of Semiconductor memory device having a voltage lowering circuit of

1997-02-05

1999-02-23

Zarabian, A

Static information storage and retrieval

Powering

36523006, G11C 134

Patent

active

058751459

ABSTRACT:
A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

REFERENCES:
patent: 5276652 (1994-01-01), Anami
patent: 5579524 (1996-11-01), Kininis

Affiliated with

Also associated with

Rating

Semiconductor memory device having a voltage lowering circuit of does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a voltage lowering circuit of, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a voltage lowering circuit of will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-312846