Semiconductor memory with improved data programming time

Details Semiconductor memory with improved data programming time Semiconductor memory with improved data programming time

1981-10-13

1984-10-16

Stellar, George G.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365219, G11C 700

Patent

active

044778848

ABSTRACT:
A semiconductor memory comprising a memory array having a plurality of memory cells, such as floating gate type MOS transistors, arranged in a matrix form with column lines and row lines, and a plurality of bit outputs. The plurality of column lines are associated with each bit output. A circuit is provided which applies a program voltage to a plurality of column lines corresponding to each bit output in response to address signals or control signals. A plurality of memory cells corresponding to each bit output are programmed simultaneously by the circuit.

REFERENCES:
patent: 4079462 (1978-03-01), Koo
patent: 4130900 (1978-12-01), Watanabe

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