Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1990-03-15
1991-08-13
Bowler, Alyssa H.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36523003, 36523004, 365220, 365219, G11C 700, G11C 11409, G11C 11416
Patent
active
050401491
ABSTRACT:
A semiconductor memory includes an input buffer means for storing inputted data, an output buffer means for storing the data and for outputting the data and a storage means for storing the data outputted from the input buffer means and for transferring the data to the output buffer means. The input buffer means includes a plurality of memories having equal capacity. The output buffer means also includes a plurality of memories having equal capacity. The memory means have memory capacity of a divisor of memory capacity per line of the storage means. In addition, the semiconductor memory can also include a dividing means for dividing image data outputted from said input buffer into smaller data units to be written on said storage means and a recombining means for said smaller data units outputted from said storage means to supply to said output buffer means.
REFERENCES:
patent: 4541075 (1985-09-01), Dill et al.
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4567579 (1986-01-01), Patel et al.
patent: 4608671 (1986-08-01), Shimizu et al.
patent: 4630230 (1986-12-01), Sundet
patent: 4648077 (1987-03-01), Pinkham et al.
patent: 4688197 (1987-08-01), Novak et al.
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4725987 (1988-02-01), Cates
patent: 4747081 (1988-05-01), Heilveil et al.
patent: 4777624 (1988-10-01), Ishizawa et al.
patent: 4789960 (1988-12-01), Willis
Wescon Technical Papers, vol. 16, 19th-22nd Sep. 1972, pp. 413.1-413.5; Y. Hsia: "Memory Applications of the MNOS", p. 413.3, left-hand column, line 23, p. 413.4, left-hand column, line 10.
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, Dec. 1984, pp. 999-1007; R. Pinkham et al: "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications", FIGS. 1,6, p. 999, line 14, line 10; p. 1003, line 15, line 21.
Patent Abstracts of Japan, vol. 7, No. 249 (P234[1384], 5th Nov. 1983; & JP-A-58 133 698 (Nippon Denki K.K.) 09-08-1983.
SMPTE Journal, vol. 89, No. 4, Apr. 1984, pp. 257-262; T. Yoshino et al: "Digital Frame Memory for Still Picture Television Receivers PASS Encoding System and Application", FIG. 15, p. 261, col. 3, line 17, p. 262, col. 1, line 19.
Ebihara Norio
Kita Hiroyuki
Ohsawa Yoshihito
Sasaki Takayuki
Bowler Alyssa H.
Kananen Ronald P.
Sony Corporation
LandOfFree
Semiconductor memory with divided readout from storage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory with divided readout from storage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory with divided readout from storage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1532350