Semiconductor memory with a plurality of memory banks

Details Semiconductor memory with a plurality of memory banks Semiconductor memory with a plurality of memory banks

2000-04-14

2001-05-01

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

06226219

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor memory with memory banks, which can be selected by associated memory bank decoders.
Memory cells in semiconductor memories are arranged in matrix form, that is to say in rows and columns. Address decoders are in each case provided for rows and columns, and allow one of the rows or columns to be selected. Normally, the memory cells are activated in rows via word lines by switching on access transistors via which in each case one capacitor is accessed, in which the information in the memory cell is stored. The line path of the transistors is connected in columns to bit lines via which the information in a memory cell can be read, after having been amplified with a read amplifier. Access for writing information to be stored to a memory cell takes place in a corresponding manner.
In very modern semiconductor memories using dynamic memory cells (DRAMs), the memory cell array has a bank architecture.
A memory bank contains all those functional units which are required to carry out a memory access autonomously. A memory bank is thus assigned respective row and column address decoders, together with read amplifiers and other functional units required for operation of the semiconductor memory, for example time control circuits, redundancy circuits etc. If necessary, functional units in different memory banks may be used jointly, for example read amplifiers or bit line or column decoders.
A memory bank and the functional units associated with it are activated by memory bank decoders. When access to a specific memory cell in a memory bank is intended, the functional units associated with the memory bank are switched from a waiting state or standby to an activated state. The actuation process is brought about by a memory bank decoder output signal associated with that memory bank. Each memory bank has a unique memory bank address assigned to it. When the address is applied to the memory bank decoder, the output signal of the latter associated with the memory bank is activated.
As the number of memory banks increases, the memory bank decoders become more complex. By way of example, a DRAM with a memory capacity of 64 Mbits comprises 16 memory banks, and a DRAM with 128 Mbits and a corresponding architecture comprises 32 memory banks.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor memory with memory banks which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and in which the design complexity required for the memory bank decoders is low.
With the above and other objects in view there is provided, in accordance with the invention, a semiconductor memory, comprising:
a plurality of memory banks divisible into a first group of memory banks and a second group of memory banks, each of the memory banks including
a memory cell field in which a multiplicity of memory cells are arranged in a matrix;
an address decoder connected to the memory cells for selecting a row in the matrix of memory cells; input devices for supplying an address with a number of
address bits and defining a selection of a respective row in one of the memory cells by actuating the address decoder;
a first memory bank decoder having an input side connected to receive a first portion of the address bits and a first enable signal, and an output side connected to the first group of memory banks, the first memory bank decoder outputting a respective bank selection signal for each the memory bank in the first group, for selecting one of the memory banks in the first group;
a second memory bank decoder constructed substantially identically to the first memory bank decoder and connected to the second group of memory banks, the second memory bank decoder having an input side connected to receive the first portion of the address bits and a second enable signal, and an output side outputting a respective bank selection signal for each the memory bank in the second group, for selecting on of the memory banks in the second group; and
a predecoder having a logic circuit, an input side connected to receive a second portion of the address bits and a further enable signal, and an output side outputting the first and second enable signals as mutually complementary signals.
In accordance with an added feature of the invention, the memory bank decoders each include a memory bank decoder element for each associated memory bank, each the memory bank decoder element having an input side connected to receive the first portion of the address bits and the respective enable signal.
In accordance with an additional feature of the invention, the predecoder includes logic gate elements each having an output outputting the complementary enable signals, and an input connected to receive the further enable signal and complementary signals of the second portion of the address bits.
In accordance with another feature of the invention, the memory banks are activatable and deactivatable by the bank selection signal output by the address decoders.
In accordance with a further feature of the invention, the address decoders are connected to receive a third portion of the address bits, and the address bits in the third portion of the address bits are identical for all the memory banks.
In accordance with an advantageous embodiment of the invention, the plurality of memory banks are 2
m
different memory banks, the first portion of the address bits has n different address bits, the second portion of the address bits has m−n different address bits, the first and second memory bank decoders are included in a number 2
m−n
of memory bank decoders each having 2
n
memory bank decoder elements, an output signal of a respective the memory bank decoder element of one of the memory bank decoders is activated when one specific combination of 2
n
possible combinations of states of the address bits input to the respective the memory bank decoder occurs, each of the memory bank decoder elements in a given the memory bank decoder is activatable by a different combination, and m and n are integers.
In accordance with a concomitant feature of the invention, the memory banks associated with one of the first and second memory bank decoders are disposed immediately adjacent one another.
In summary, a number of identical memory bank decoders are arranged in a semiconductor memory according to the invention. A predecoder is used to switch between these memory bank decoders. The layout of an individual memory bank decoder is known from a memory generation with a smaller memory capacity. This is transferred to the following design of a semiconductor memory having a higher capacity. If need be, the layout can automatically be restricted to a lower structure width of the production process. The additional design complexity occurs in the design of the predecoder, to the input side of which the address signals which are additionally necessitated by the greater memory capacity are supplied.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory having memory banks, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5357478 (1994-10-01), Kikuda et al.
patent: 5742554 (1998-04-01), Fujioka
patent: 5774409 (1998-06-01), Yamazaki et al.
patent: 5844857 (1998

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