Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-07-11
1999-02-02
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523006, G11C 700
Patent
active
058674330
ABSTRACT:
Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.
REFERENCES:
patent: 5257229 (1993-10-01), McClure et al.
patent: 5471426 (1995-11-01), McClure
patent: 5570318 (1996-10-01), Ogawa
patent: 5596535 (1997-06-01), Mushya et al.
patent: 5642316 (1997-06-01), Tran et al.
patent: 5657280 (1997-08-01), Shin et al.
patent: 5689463 (1997-11-01), Murakami et al.
Ho Jiang-Hong
Kirsch Howard Clayton
Kuo Jack-Lian
Lin Yen-Tai
Shen Chiun-chi
Ackerman Stephen B.
Dinh Son T.
Satle George O.
Vanguard International Semiconductor Corporation
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