Semiconductor memory with a data holding circuit having two...

Details Semiconductor memory with a data holding circuit having two... Semiconductor memory with a data holding circuit having two...

2006-09-19

2006-09-19

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S094000

Reexamination Certificate

active

07110307

ABSTRACT:
An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.”

REFERENCES:
patent: 6798698 (2004-09-01), Tanaka et al.
patent: 2003/0035316 (2003-02-01), Tanaka et al.
patent: 2003/0147286 (2003-08-01), Tanaka et al.
patent: 61255035 (1986-11-01), None
patent: 04034799 (1992-02-01), None
patent: 06176592 (1994-06-01), None

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