Semiconductor memory using low power supply voltage

Details Semiconductor memory using low power supply voltage Semiconductor memory using low power supply voltage

1994-04-05

1995-08-01

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365207, 365208, G11C 700

Patent

active

054385431

ABSTRACT:
A peripheral/refresh control circuit for a semiconductor memory device, e.g., a dynamic random access memory (DRAM), which includes a first pull-up device connected between a supply voltage and the pull-up node of a sense amplifier, the first pull-up device having a first mode of operation wherein the power supply voltage is coupled to the pull-up node and a second mode of operation wherein the power supply voltage is isolated from the pull-up node, a second pull-up device coupled between a boosting voltage and the pull-up node, the second pull-up device having a first mode of operation wherein the boosting voltage is coupled to the pull-up node and a second mode of operation wherein the boosting voltage is isolated from the pull-up node, a first pull-up control circuit for selectively switching the first pull-up device between its first and second modes of operation, and a second pull-up control circuit for selectively switching the second pull-up device between its first and second modes of operation.

REFERENCES:
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4625300 (1986-11-01), McElroy
patent: 4951256 (1990-08-01), Tobita
patent: 5127739 (1992-07-01), Duvvury et al.
patent: 5162681 (1992-11-01), Lee

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