Semiconductor memory using dynamic ram cells

Details Semiconductor memory using dynamic ram cells Semiconductor memory using dynamic ram cells

1988-11-23

1990-07-24

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365210, 365149, G11C 700

Patent

active

049439448

ABSTRACT:
Bit-line pairs and word lines are disposed perpendicular to one another and dRAM cells are placed at their intersections. A dummy cell is connected to each of the bit-line pairs. A bit-line sense amplifier and an equalizer are connected to one end of the bit-line pair. The other end of the bit-line pair is connected to a latch type memory cell via a first transfer gate. The latch type memory cell are further connected to input/output line pair via a second transfer gate controlled by a column select line. During a RAS active period in a read cycle a word line is selected so that data is read from a dRAM cell and the dummy cell connected to the selected word line onto the bit-line pairs. The bit-line sense amplifiers are activated so that the levels of the bit lines become determinate. The first transfer gates are subsequently turned on to transfer the data on the bit-line pairs to the latch type cells. After the memory cells are rewritten into, the selected word line is reset and the latch type memory cells are electrically disconnected from the bit-line pairs. The equalizers operate to precharge the bit-line pairs. When CAS is rendered active and a column is selected, a corresponging second transfer gate is turned on so that data in the latch type memory cell is read out onto the input/output line pairs.

REFERENCES:
patent: 4758987 (1988-07-01), Sakui
patent: 4780850 (1988-10-01), Miyamoto et al.

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