Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-08-08
2004-12-28
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S723000, C365S185290, C365S201000
Reexamination Certificate
active
06836863
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor memory, in particular, to a semiconductor memory testing method and apparatus which is used to determine whether a flash memory, in a preferred application, is acceptable or faulty.
FIG. 1
schematically illustrates a semiconductor memory testing apparatus which is commonly employed.
The semiconductor memory testing apparatus comprises a timing generator
11
, a pattern generator
12
, a waveform shaper
13
, and a logic comparator
14
in order to test a memory under test MUT for a normal operation.
Specifically, the timing generator
11
generates a reference clock, which is used by the pattern generator
12
in developing address signal, test pattern data and control signals which are to be applied to the memory MUT. Initially, these signals are applied to the waveform shaper
13
, which operates to shape them into waveforms which are required to conduct the test, and then are applied to the memory MUT.
The control signal controls a writing into or a read-out from the memory MUT of the test pattern data. Test pattern data which is read from the memory MUT is applied to the logic comparator
14
where the read data is compared against expected value data delivered from the pattern generator
12
to see if both match or do not match, thus determining whether the memory MUT is acceptable or faulty. The result of determination rendered is fed back to the pattern generator
12
to be used in aborting the test or in modifying a sequence of patterns generated.
The pattern generator
12
stores “fail” information sent from the logic comparator
14
, and such “fail” information allows the sequence of patterns generated to be modified. A functional arrangement of a generated pattern sequence controller which is capable of modifying the sequence of patterns generated is schematically shown in FIG.
2
.
Specifically, a generated pattern sequence controller
12
A comprises a “fail” latch
121
and a sequence controller
122
. “Fail” information FL and a clear signal CLE are input to the fail latch
121
. Fail information FL is delivered from the logic comparator to be latched or stored in the fail latch
121
. The clear signal CLE is effective to clear or erase the information latched in the fail latch
121
. An instruction which causes the clear signal to be issued can be described in a pattern generating program at any cycle, and thus the clear signal can be issued at any cycle during the test cycle.
The sequence controller
122
comprises a storage (program memory
122
a
) containing a sequence instruction (a generated pattern sequence program) which allows the sequence of patterns generated to be modified in accordance with the fail information stored in the fail latch
121
, and a controller
122
b
which executes a program in the storage.
A flash memory is one of varieties of semiconductor memory, and exhibits a non-volatile feature which retains its stored content if the power supply thereto is interrupted. The flash memory has an internal arrangement comprising a plurality of memory blocks, and can be erased in unit of a memory block or an entire chip by a batch operation. As termed herein, a semiconductor memory in which an entire chip is erased by a batch operation will be described as “a semiconductor memory comprising only a single memory block”.
The flash memory is provided with a charging function for each memory cell, and this charging function allows the stored content to be maintained if the power supply is interrupted. As a result of the presence of such function, immediately after the manufacture, the flash memory contains memory cells having their charging functions which are aligned with each other in a normal manner and memory cells having their charging functions which are out of the normal range. Accordingly, the flash memory is subject to an erasure by a batch operation in unit of a block or an entire chip, thus bringing individual memory cells to their normal condition or a storage of logic “1”. However, it is not assured that a single erasure operation can bring all of the memory cells to a normal condition.
For this reason, an erasure operation of a flash memory is conducted immediately after its manufacture, and is followed by a read-out test (confirmation test) which is intended to detect any memory cell which remains unerased (or offset from a normal condition). The combination of the erasure operation and the read-out test is referred to as an erase test, and is repeatedly conducted.
During the erase test, if memory cell is detected which remains unerased, the erasure operation is again conducted for the memory block which includes the cell, and a confirmation is again made to see the stored content of the cell. The erase operation and the confirmation operation are repeated until there is no memory cell which remains unerased. A memory block is determined to be “pass” (acceptable) if the erasure of all memory cells of the memory block is completed when the erase test is repeated within a prescribed number of repetitions. A memory block is described to be “fail” (faulty) if the erasure of memory cells of the block is not completed when the erase test is repeated the prescribed number of repetitions, and the procedure proceeds to testing a next memory block. Alternatively, if the memory block found to be “fail” is a last memory block to be tested, the test is terminated.
FIG. 3
schematically illustrates a processing procedure followed by the sequence controller
122
. At step SP
0
, a variable M is set to 1 and the address of a memory block under test (which may be hereafter simply refereed to as “block”) is initialized. At next step SP
1
, the pattern generator
12
(see
FIG. 1
) is caused to apply an erasure pulse to the block under test, thus conducting an erasure operation. At step SP
2
, the pattern generator
12
is caused to conduct a read-out test from the block. The read-out test takes place from the leading address to the final address of the memory block.
At step SP
3
, a determination is rendered as to whether or not a “fail” has occurred (or if there is an unerased memory cell) during the read-out test. If no “fail” occurs, a determination is rendered at step SP
4
as to whether this memory block is the final memory block. If it is, the procedure is completed. If it is not, the procedure goes to step SP
5
which prepares for the transfer to the testing of the next following memory block, thus returning to step SP
1
where the testing of the next memory block is initiated.
In the event the occurrence of a “fail” is determined at step SP
3
(or if fail information latched in the fail latch
121
is found), the procedure branches to step SP
6
where the variable M, which determines a maximum number of times the erasure operation and the read-out test are repeated, is incremented by one. At step SP
7
, a determination is rendered as to whether the variable M has exceeded a preset number of times, which is chosen to be “20” in the example shown. If the variable M is less than 20, the procedure returns to step SP
1
, thus again conducting the erasure operation and the read-out test upon the same memory block. When the repetition exceeds 20, M>20 is satisfied, whereby a determination is rendered at step SP
8
that the memory block being tested is “fail”, subsequently transferring to step SP
4
. The counting of the variable M takes place within the sequence controller
122
.
In this manner, the sequence controller
122
of the prior art is structured such that it is only capable of repeating the erasure operation and the read-out test if only one “fail” occurs during the read-out test.
As described, the erasure operation and the read-out test are repeated as long as an unerased memory cell is detected according to the prior art practice, and thus it follows that a memory block or a chip containing an increased number of unerased memory cells requires an increased number of repeated erasure operations and read-out tests, disadvantageously resulting in an increased length of time
Okino Noboru
Tabata Makoto
Advantest Corporation
Dildine R. Stephen
Gallagher & Lathrop
Lathrop, Esq. David N.
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