Semiconductor memory testing device

Details Semiconductor memory testing device Semiconductor memory testing device

2006-04-11

2006-04-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S048000, C714S799000, C365S201000

Reexamination Certificate

active

07028236

ABSTRACT:
This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular memory block after a failure is detected in the block. The test system which tests writing and erasing as a unit of block in the memory under test. The test system includes a register provided for each memory under test for holding a first failure generated in a particular block at a first control signal from a pattern generator, establishes a pass result for the particular block for test cycles after the first failure, thereby treating any failure result for the particular block as the pass result thereafter; and resets the register at a cycle specified by a second control signal from the pattern generator to release the pass result.

REFERENCES:
patent: 5412662 (1995-05-01), Honma et al.
patent: 5604756 (1997-02-01), Kawata
patent: 5646948 (1997-07-01), Kobayashi et al.
patent: 5673271 (1997-09-01), Ohsawa
patent: 7-130200 (1995-05-01), None
patent: 7-192497 (1995-07-01), None
patent: 8-55498 (1996-02-01), None

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