Semiconductor memory testing apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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714 25, G01R 3128

Patent

active

061382590

ABSTRACT:
In a semiconductor memory testing apparatus for testing a DRAM which requires a refresh operation, plural pattern generation parts are operated normally to generate high-speed pattern signals. The plural pattern generation parts are connected to a common sequence control part and controlled by the count value of the same program counter so that they branch to the refresh mode, operate in the refresh mode a plurality of number of times, then return to the main routine and resume the generation of pattern data.

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