Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-07-30
2011-11-08
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
08055978
ABSTRACT:
A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.
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Korean Office Action dated Jan. 28, 2008 from corresponding Korean Patent Application No. 10-2007-0008911.
Kim Ki Hong
Kim Sun Kwon
Lee Byeong Hoon
Lee Seung Won
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
Torres Joseph D
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