Semiconductor memory system and wear-leveling method thereof

Details Semiconductor memory system and wear-leveling method thereof Semiconductor memory system and wear-leveling method thereof

2008-12-12

2011-11-08

Gu, Shawn X (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S156000, C711S165000, C711S170000

Reexamination Certificate

active

08055836

ABSTRACT:
Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type.

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patent: 2002/0199129 (2002-12-01), Bohrer et al.
patent: 2007/0294490 (2007-12-01), Freitas et al.
patent: 2001-0029171 (2001-04-01), None
patent: 10-2005-0050148 (2005-05-01), None
patent: 10-2005-0059314 (2005-06-01), None

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