Semiconductor memory storage electrode and method of making

Details Semiconductor memory storage electrode and method of making Semiconductor memory storage electrode and method of making

2000-06-27

2002-04-02

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C438S241000

Reexamination Certificate

active

06365928

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing storage electrodes in a semiconductor memory device and a structure of those storage electrodes, and more particularly to a structure and method for manufacturing storage electrodes of dummy cells arranged at the peripheral portion of a cell region in a semiconductor memory device.
2. Description of the Prior Art
Semiconductor memory devices are mainly classified into products of a random access memory (RAM) type having a data volatility and products of a read only memory (ROM) type having no data volatility. In the case of a semiconductor memory device, which is of the RAM type and includes one access transistor and one capacitor, as in a dynamic RAM (DRAM), the data storing ability depends on the capacitance of the capacitor. For this reason, if such a semiconductor memory device has an insufficient capacitance, it may involve data errors. That is, data previously stored in the semiconductor memory device may be erroneously read out. In order to avoid such data errors in such a semiconductor memory device, it is necessary to periodically conduct a refresh operation adapted to store again the previously stored data after a predetermined period of time elapses. An increase in capacitance may improve refresh characteristics since the refresh operation is effected by the capacitance. However, this is impractical for recently developed high density semiconductor memory devices having reduced unit cell area. Such a reduction in the unit cell area decreases in the area where a capacitor is formed.
Generally, capacitance is proportional to the surface area where a storage electrode serving as a lower electrode and a plate electrode serving as an upper electrode are in spaced relation with each other while being inversely proportional to the distance between those two electrodes. In order to form a storage electrode having a surface area as large as possible within a limited area on the chip, a method has been proposed in which a capacitor under bit-line (CUB) structure formed with a capacitor under a bit line is also formed with a capacitor over the bit line using a capacitor over bit-line (COB) process, so that a stacked capacitor having a three-dimensional structure, such as a cylindrical, box, or pin type, is manufactured.
FIG. 1
is a schematic plan view illustrating a typical semiconductor device. As shown in
FIG. 1
, the semiconductor device includes a plurality of cell regions divided from one another by a peripheral circuit region. In
FIG. 1
, the reference character “A” denotes a boundary area between one cell region and the peripheral circuit region. In such boundary areas, diverse dummy patterns, such as dummy gates, dummy bit lines, and dummy capacitors, are typically formed. Although such dummy patterns are not associated with practical operations, they are provided to ensure the reliability of main cells and to achieve an improvement in resolution in a photolithography process. In recently developed semiconductor memory devices having storage electrodes with an increased height, thereby obtaining a higher capacitance with greater packing density, the increased height of those storage electrodes may cause a problem in that the storage electrode patterns of dummy cells arranged in the boundary area “A”, between the cell region and peripheral circuit region, are smaller than a desired size due to a loading effect produced during formation thereof that may them to collapse. Where the storage electrode patterns collapse, a bridge phenomenon occurs, which results in a short circuit between adjacent storage electrodes. In order to solve this problem, a method has also been proposed in which the storage electrodes of dummy cells are connected together to form a single pattern.
FIG. 2
is a schematic enlarged plan view corresponding to the portion “A” of FIG.
1
.
Referring to
FIG. 2
, a cell region typically includes main cells and dummy cells. The dummy cells are arranged at the peripheral portion of the cell region in order to ensure the reliability of the main cells. Respective storage electrodes of the dummy cells are connected together in a bit line direction (the horizontal direction in
FIG. 2
) and in a word line direction (the vertical direction in
FIG. 2
) so that they form a single large pattern. In detail, the storage electrodes in each of two dummy cell lines extending in the bit line direction are connected together, whereas the storage electrodes of one dummy cell line extending in the word line direction are connected together.
FIG. 3
is a layout diagram corresponding to FIG.
2
.
Referring to
FIG. 3
, a semiconductor substrate (not shown), which is included in a semiconductor device defined with cell regions and a peripheral circuit region while having main cells and dummy cells at each cell region, is defined with an active region
11
at a desired portion thereof, and a field region (not shown) at the remaining portion thereof. A plurality of uniformly spaced word lines
14
are formed on the substrate in such a fashion that they extend vertically. A plurality of uniformly spaced bit lines
21
are also formed on the substrate in such a fashion that they extend in perpendicular to the word lines
14
.
Landing pads
18
are formed at desired portions of active region
11
, that is, common drain regions, between adjacent ones of word lines
14
so that they provide direct contacts DC adapted to electrically connect those common drain regions to associated ones of bit lines
21
. At respective portions of active region
11
corresponding to source regions, landing pads
18
are also formed between adjacent ones of word lines
14
so that they provide buried contacts BC adapted to electrically connect those source regions to respective storage electrodes
24
of capacitors formed on the substrate. Storage electrodes
24
are provided for the main cells and dummy cells of the semiconductor device, respectively. Storage electrodes
24
of the dummy cells extending in two lines in the bit line direction while extending in one line in the word line direction are connected together in the form of a single pattern. On the other hand, storage electrodes
24
of the main cells are arranged in a matrix array and connected to buried contacts BC, respectively.
FIG. 4
is a cross-sectional view taken along a line B-B′ of
FIG. 3
, that is, the bit line direction.
FIG. 5
is a cross-sectional view taken along a line C-C′ of
FIG. 3
, that is, the word line direction.
Referring to
FIGS. 3
to
5
, a semiconductor substrate
10
, which has main cell regions and dummy cell regions, is first prepared and then defined with an active region
11
and a field region. A field oxide film
12
is then formed on the field region of semiconductor substrate
10
. Access transistors, each of which includes a word line
14
and a spacer insulating film
16
, are also formed on active region
11
of semiconductor substrate
10
. A landing pad
18
is arranged on a desired portion of each access transistor, that is, a source region
17
. Landing pad
18
is formed by etching a first interlayer insulating film
20
formed over semiconductor substrate
10
, after the formation of the access transistors, in such a fashion that the associated source region
17
is exposed, and then filling an appropriate landing pad material on the exposed source region
17
. Storage electrodes
24
for respective dummy cells are arranged in the form of a single pattern on respective landing pads
18
for the access transistors of those dummy cells. Storage electrodes
24
are formed by etching a second interlayer insulating film
22
, formed over the structure obtained after the formation of landing pads
18
, in such a fashion that the associated landing pads
18
are exposed, and then filling an appropriate storage electrode material on the exposed landing pads
18
. Storage electrodes
24
are not separated from one another, but connected together in the form of a single patte

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