Semiconductor memory provided with data-line equalizing circuit

Details Semiconductor memory provided with data-line equalizing circuit Semiconductor memory provided with data-line equalizing circuit

2001-04-23

2002-04-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189090, C365S230060

Reexamination Certificate

active

06373763

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, particularly to a semiconductor memory provided with a data-line equalizing circuit for setting each data line constituting a data-line pair to the same predetermined voltage before reading data from a memory cell.
2. Description of the Background Art
In the case of a dynamic random access memory (DRAM), the equalizing operation for setting each data line constituting a data-line pair for transferring stored data to the same predetermined voltage is performed before reading data from a memory cell.
FIG. 12
is a circuit diagram showing a configuration of the circumference of a data-line equalizing circuit (hereafter also merely referred to as equalizing circuit) of a conventional DRAM.
Referring to
FIG. 12
, a memory cell MC for keeping stored data has an access transistor AT and a storage capacitor SC for keeping a voltage level of a data storage node Nm.
FIG. 12
shows the so-called shared-sense-amplifier configuration, and a sense-amplifier circuit SA is shared by data-line pairs DRP and DLP separately arranged. The stored data of one memory cell MC typically shown in
FIG. 12
is transferred by the data-line pair DRP. The data-line pair DRP has a data line DR electrically connected with a data storage node Nm in the memory cell MC through the access transistor AT and a data line /DR for transferring the data complementary with the data line DR. Similarly, the data-line pair DLP has a data lines DL and /DL for transferring the data complementary with each other.
In the case of a DRAM conforming to the shared-sense-amplifier configuration, switching circuits
6
and
7
for connecting/disconnecting two data-line pairs DRP and DLP with/from the sense-amplifier circuit SA are set between the pairs DRP and DLP on one hand and the circuit SA on the other. The switching circuits
6
and
7
are respectively constituted of an N-channel MOS transistor. Specifically, the switching circuit
6
has N-channel MOS transistors M
1
L and M
2
R receiving a control signal DLIR by their gates. Similarly, the switching circuit
7
has N-channel MOS transistors M
1
L and M
2
L receiving a control signal DLIL by their gates.
The data-line pairs DRP and DLP further share an equalizing circuit
8
. The equalizing circuit
8
has an N-channel MOS transistor M
3
for connecting both data lines constituting a data-line pair and N-channel MOS transistors M
4
and M
5
for connecting each data line constituting a data-line pair with a predetermined precharge-voltage (Vdd/2) node. A data-line-equalizing signal DLEQ is input to gates of the transistors M
3
, M
4
, and M
5
.
A precharge voltage is generally set to Vdd/2 which is an intermediate voltage between a power-supply voltage Vdd corresponding to H level of stored data and a ground voltage Vss corresponding to L level of the stored data in order to reduce the power consumption and noises accompanying charge/discharge of a data line.
An external power-supply voltage ExVdd is supplied to a DRAM from the outside of a chip. A power-supply voltage Vdd stepped down from ExVdd by a not-illustrated VDC (Voltage Down Converter) or a step-up voltage Vpp (Vpp>Vdd) stepped up from ExVdd by a Vpp generation circuit
2
are generated in the DRAM.
The transistors used for switching circuits
6
and
7
, equalizing circuit
8
, and access transistor AT are frequently respectively constituted of only an N-channel MOS transistor in order to reduce an area. In this case, to transfer the power-supply voltage Vdd corresponding to H level of stored data, it is necessary to set the gate voltage of an N-channel MOS transistor to Vdd+Vth (Vth: threshold voltage of N-channel MOS transistor) or higher.
Therefore, the step-up voltage Vpp (Vpp>Vdd) is used for each H-level potential of control signals DLIR and DLIL input to the gate of an N-channel MOS transistor constituting the switching circuits
6
and
7
. Specifically, the control signals DLIR and DLIL are generated by signal buffers
3
and
4
driven by the step-up voltage Vpp.
Also for a word line WL for turning on the access transistor AT, an activated voltage level is set to the step-up voltage Vpp by a word-line driver WD driven by the step-up voltage Vpp.
It is only necessary for the N-channel MOS transistors M
3
to M
5
constituting the equalizing circuit
8
to transfer the precharge voltage Vdd/2 of a data line. Therefore, it is unnecessary to use a step-up voltage for a voltage when a data-line equalizing signal DLEQ input to gates of these transistors is activated, that is, an H-level voltage as long as the H-level voltage meets the following expression (1).
ExVdd>Vth+Vdd/
2  (1)
Therefore, a signal buffer
5
for generating the data-line equalizing signal DLEQ is driven by the external power-supply voltage ExVdd, and the H-level voltage of the data-line equalizing signal DLEQ has been generally set to ExVdd.
FIG. 13
is a timing chart for explaining the data read operation of the DRAM shown in FIG.
12
.
Referring to
FIG. 13
, the data-line equalizing signal DLEQ and control signals DLIR and DLIL are respectively activated to an H-level voltage before data is read. As already described, H-level voltages of the control signals DLIR and DLIL are respectively equal to the step-up voltage Vpp, and the H-level voltage of the data-line equalizing signal DLEQ is equal to ExVdd.
Thereby, the transistors M
1
R, M
1
L, M
2
R, M
2
L, and M
3
to M
5
constituting the switching circuits
6
and
7
and the equalizing circuit
8
are all turned on. As a result, the data lines DR and /DR are set to the same precharge voltage Vdd/2. Data lines DL/DL are also set to the same precharge voltage Vdd/2 (not shown). Thus, the equalizing operation of a data line is executed before the data read operation.
When the data read operation is started, either of the switching circuits
6
and
7
is turned on and only one data-line pair is connected with the sense amplifier SA. In
FIG. 13
, to disconnect the data-line pair DLP from the sense amplifier SA, the transistors M
1
L and M
2
L constituting the switching circuit
7
are turned off in response to inactivation (to L-level voltage Vss) of the control signal DLIL.
Similarly, the data-line equalizing signal DLEQ is inactivated to the L-level voltage (Vss), and the transistors M
3
to M
5
constituting the equalizing circuit
8
are turned off.
Under the above state, the word line WL is activated to the H-level voltage (step-up voltage Vpp). In response to the above operation, the access transistor AT is turned on, and the data storage node Nm is connected with the data line DR.
FIG. 13
shows a case in which the memory cell MC keeps H-level data. Therefore, the voltage level of the data line DR is slightly stepped up by electric charges stored in the storage capacitor SC in response to turn-on of the access transistor AT. However, the voltage level of the complementary data line /DL is kept at the precharge voltage Vdd/2.
Thereafter, the sense-amplifier circuit SA is further activated and voltage levels of power-supply nodes SP and SN are set to the power-supply voltage Vdd and ground voltage Vss. Thereby, a minute voltage difference generated between the data lines DR and /DR is amplified, and voltage levels of the data lines DR and /DR are set to Vdd and Vss. Thus, data is normally read from the DRAM by assuming the normal equalizing operation of the data lines.
As described above, the data-line-equalizing signal DLEQ for controlling the equalizing circuit
8
is generally driven by the external power-supply voltage ExVdd.
Recently, however, a DRAM is frequently mounted on portable information terminal units that have been rapidly spread. It is requested for these portable information terminal units to operate for a long time by a battery having a limited power-supply capacity. Therefore, it is requested that the power consumption of an electronic device mounted on a portable information terminal unit is minimized. Because the power con

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