Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-05-24
2002-07-23
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S686000, C257S777000, C257S723000
Reexamination Certificate
active
06424030
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device. More particularly, it relates to a semiconductor device which is so constructed that a semiconductor chip is put into the form of a module and that a plurality of semiconductor chips are mounted on a module base plate.
A semiconductor device of high packaging density, which is constructed in such a way that a plurality of packages each having a semiconductor chip molded therein are installed on a mounting base plate (a module base plate), is described in “Nikkei Electronics” issued by Nikkei McGraw-Hill Inc., Extra Issue no. 2 “Microdevices,” p. 150.
Further, the present invention relates to a technique for installing tape carriers in stacked fashion.
One of techniques for assembling semiconductor elements is the tape carrier system. This system is also termed the “film carrier” or “TAB (Tape Automated Bonding)” system, etc. It is a method wherein semiconductor elements are successively assembled on an elongate resinous tape which is provided with sprocket holes (perforation holes). The tape carrier is such that lead patterns conforming to the electrode arrangements of the semiconductor elements (chips) are formed on a resin film which has the sprocket holes and device holes. By way of example, the tape carrier is prepared via the steps of slitting a polyimide film coated with a binder, into a proper width; punching the sprocket holes for feed and the device holes for assembling the chips therein, in the slitted film; laminating the punched film with a copper foil; and forming the desired lead patterns by the use of a photoresist technique and an etching technique.
An example of the tap carrier semiconductor chip mounting technique is described in “VLSI TECHNOLOGY” 1983 copyright, p. 558, McGraw-Hill Book Company, Japan.
BRIEF SUMMARY OF THE INVENTION
However, there are problems with tape carrier chip mounting technique of prior art which the present invention solves. The specific problems, of which is it the object of the present invention to overcome, are as follows:
The footprint area of the mounted chip is difficult to reduce. Therefore, increasing the packaging density of chips per unit area on the module's base plate is difficult.
Further, regarding the prior-art tape carrier stated before, the tape carriers of one kind correspond to one predetermined layout and have the same lead patterns. Therefore, the tape carriers of the same kind cannot be installed on a mounting base plate in stacked fashion.
This poses the problem that, when the semiconductor elements are to be installed at a high density, the tape carriers of the same kind need to be juxtaposed on the mounting base plate, so wiring on the surface of the mounting base plate such as a printed-wiring circuit board becomes complicated. Moreover, wire breakage, etc. is prone to occur, and the reliability of the assembled device lowers.
An object of the present invention is to increase the packaging density of a multichip semiconductor device.
Another object of the present invention is to provide a high-density memory device which is suited to flat packaging.
Another object of the present invention is to provide a memory device which is capable of high-density packaging.
Another object of the present invention is to provide a high-density flat packaging technique which matches well with the TAB (tape automated bonding) technology. Another object of the present invention is to provide a high-density packaging method which can fully exploit the TAB technology.
Another object of the present invention is to provide a method of assembling memory devices which is capable of simplifying the assembly process and reducing labor.
Another object of the present invention is to provide a memory module which can install a large number of memory chips compactly.
Another object of the present invention is to provide a multiple chip and lead complex which exhibits a good solderability at a solder reflow step.
The aforementioned and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.
A typical aspect of performance of the present invention will be briefly summarized below:
The bump electrodes of a semiconductor chip are connected to leads, and a plurality of such semiconductor chips having the leads are connected to the wiring of a module base plate, thereby to construct a semiconductor device.
According to the above-stated expedient, the semiconductor chips are not sealed within packages, therefore the packaging density of the semiconductor chips on the module base plate can be increased.
Another typical aspect of performance of the present invention is as follows:
In the present invention, a plurality of tape carriers of an identical kind, the respective lead patterns of which are partly different, are prepared. An alteration for the difference is limited to, for example, only a lead for a chip select signal. Subsequently, the tape carriers thus having the partly different lead patterns are installed on a mounting base plate in stacked fashion.
As described above, the respective lead patterns of the tape carriers to be installed are made partly different so as to permit the stacked installation of these tape carriers, so that semiconductor elements can be installed at a high density, the wiring of the mounting base plate is simplified, and the reliability of the installed device can be enhanced.
In still another typical aspect of performance of the present invention, a semiconductor integrated circuit memory device comprises:
(a) first and second SRAM semiconductor chips each of which is either of substantially square or rectangular flat shape and has a first and second principal surface, said first principal surface being formed with major portions of an SRAM integrated circuit;
(b) a number of electrode pads which are provided near a pair of opposing latera of said first principal surface of said each chip;
(c) a chip select pad which is provided near either of said pair of opposing latera of said first principal surface of said each chip;
(d) a number of leads each of which is made of a metal sheet and an inner end of each of which is connected with a corresponding one of said large number of electrode pads of said each chip;
(e) first and second leads each of which is made of a metal sheet and inner ends of which are connected with the chip select pads of said respective chips;
(f) an insulator member which is interposed between said second principal surface of said first chip and said first principal surface of said second chip extending near the former substantially in parallel therewith; and
(g) superposed connection portions in which parts of and near outer ends of said large number of leads corresponding to said electrode pads having the same functions are respectively superposed and connected so that their extending directions may agree.
In yet another typical aspect of performance of the present invention, a method of assembling a semiconductor integrated circuit wherein memory chips are respectively assembled into a large number of semiconductor chip mounting openings which are provided along a central part of a carrier tape, by connecting them through bump electrodes, comprising:
(a) the step of gang-bonding memory chips having either of the same patterns or substantially the same patterns, to first and second carrier tapes through bump electrodes, respectively, where each of said first and second carrier tapes has a number of leads made of metal sheets on a first principal surface and in a chip mounting opening, and said first and second carrier tapes have either of substantially the same patterns or the same patterns, except leads which are to be respectively connected with either of chip select terminals and terminals equivalent thereto;
(b) the step of gang-bonding memory chips having either of the same patterns or substantially the same patterns, to corresponding openings of such first and second carrier tapes through bump elect
Masayuki Watanabe
Seiichiro Tsukui
Takashi Ono
Toshio Sugano
Yoshiaki Wakashima
Clark Jhihan B
Hitachi , Ltd.
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