Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1987-10-27
1989-07-18
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365210, 365203, 365204, G11C 700
Patent
active
048499358
ABSTRACT:
A semiconductor memory having latch circuits, each of which is coupled to receive the potential of a bit line and which can operate, in response to a control signal, in either a through mode or a latch mode. In the through mode, the latch circuit outputs the potential of the bit line. In the latch mode, it latches this potential and then outputs it. The memory further comprises a dummy bit line and FETs. These FETs are provided at the intersections of the dummy bit line and all word lines of the memory. Hence, the dummy bit line is discharged whenever a word line has been selected. The latch circuits, which are provided in the output section of the memory, are set to the through mode when the dummy bit line is discharged to a predetermined potential.
REFERENCES:
patent: 4044341 (1977-08-01), Stewart et al.
patent: 4334157 (1982-06-01), Ferris
patent: 4627032 (1986-12-01), Kolwicz et al.
patent: 4644501 (1987-02-01), Nagasawa
patent: 4661927 (1987-04-01), Graebel
patent: 4750839 (1988-06-01), Wang et al.
S. Muroga, "Mask-Programmable ROM", VLSI System Design, Chapter 6, Sec. 4, 1982.
Gossage Glenn A.
Hecker Stuart N.
Kasuhiki Kaisha Toshiba
LandOfFree
Semiconductor memory including transparent latch circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory including transparent latch circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory including transparent latch circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-177194