Semiconductor memory including an intermediate potential circuit

Details Semiconductor memory including an intermediate potential circuit Semiconductor memory including an intermediate potential circuit

1999-11-23

2000-10-24

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518907, G11C 1604

Patent

active

061377317

ABSTRACT:
A semiconductor memory enables establishment of intermediate electric potential of bus line to be implemented without flowing through current between a power-supply and ground. When a read-bus line `RB` is of `Low` state, high-pulse is outputted as an internal pulse signal `RBEQ`, then `N`-type transistor N2 and `P`-type transistor P2 become `ON` state. Further, also `N`-type transistor N5 becomes `ON` state. Then, `N`-type transistor N3 becomes `OFF` state, `N`-type transistor N4 becomes `ON` state, also `P`-type transistors P3, and P4 become `ON` state. According to this situation, output of an inverter I2 becomes `Low`, `P`-type transistor P1 becomes `ON` state, `N`-type transistor N1 becomes `OFF` state, thus electric potential of the read-bus line `RB` changes into `High` from `Low`. Subsequently, it makes signal `RBEQ` `Low`, then, `P`-type transistor P2 and `N`-type transistor N2 become `OFF` state so that the read-bus line `RB` maintains intermediate potential level.

REFERENCES:
patent: 5500820 (1996-03-01), Nakaoka
patent: 5729152 (1998-03-01), Leung et al.
patent: 6055210 (2000-04-01), Setogawa

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