Semiconductor memory having single path data pipeline for CAS-la

Details Semiconductor memory having single path data pipeline for CAS-la Semiconductor memory having single path data pipeline for CAS-la

1998-08-25

1999-09-28

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Multiplexing

36523002, 365233, G11C 700

Patent

active

059598999

ABSTRACT:
In a semiconductor dynamic random access memory, a single path data pipeline for applying voltages from a sense amplifier to a data output pad for different column address signal (CAS) latencies comprising: a dual input single output latch, the dual inputs coupled to data bit (S1) and data bit bar (S1) outputs of a sense amplifier and producing a single bit data output in response thereto, a buffer circuit coupled to the output latch and operable in response to enable signals (EN, EN) for passing the data output from the latch, a dual input multiplexer (mux) with each input having a circuit for receiving the data output from the buffer circuit, one input circuit including a delay circuit for delaying application of the data output from the buffer circuit to the mux, the mux operable in response to a column address (CAS) latency signal to pass one of two signals, and logic gates coupled to pass the mux output to control the application of a voltage to a data output pad.

REFERENCES:
patent: 5877990 (1999-03-01), Kim

Affiliated with

Also associated with

Rating

Semiconductor memory having single path data pipeline for CAS-la does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory having single path data pipeline for CAS-la, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory having single path data pipeline for CAS-la will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-711226