Semiconductor memory having redundancy circuit with means to swi

Details Semiconductor memory having redundancy circuit with means to swi Semiconductor memory having redundancy circuit with means to swi

1991-11-06

1993-11-16

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 700, G11C 2900

Patent

active

052629937

ABSTRACT:
In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

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MacDonald et al., "Dynamac RAMs-200 Mbit Wafer Memory", ISSCC Digest of Technical Papers, pp. 240-241, Feb. 1989.

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