Semiconductor memory having error correction

Details Semiconductor memory having error correction Semiconductor memory having error correction

2008-01-29

2008-01-29

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Testing of error-check system

C714S746000, C714S718000, C714S025000, C714S030000, C714S734000, C365S201000

Reexamination Certificate

active

07325173

ABSTRACT:
During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.

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