Semiconductor memory having electrically erasable and programmab

Details Semiconductor memory having electrically erasable and programmab Semiconductor memory having electrically erasable and programmab

1998-05-28

2000-04-18

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518503, 36523003, G11C 1604

Patent

active

060523158

ABSTRACT:
A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.

REFERENCES:
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5771194 (1998-06-01), Maeno
M. Bauer et al., "TA 7.7: A multi-level-cell 32Mb flash memory", ISSCC95/Feb. 16, 1995/Digest of Technical Papers: Session 7, INTEL Corp., pp. 132-133.

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