Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-04-28
2010-02-16
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S259000
Reexamination Certificate
active
07662687
ABSTRACT:
A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
REFERENCES:
patent: 6239465 (2001-05-01), Nakagawa
patent: 6794249 (2004-09-01), Palm et al.
Kuesters Karl Heinz
Ludwig Christoph
Mikolajick Thomas
Schulze Norbert
Willer Josef
Dicke Billig & Czaja, PLLC
Henry Caleb
Infineon - Technologies AG
Pham Thanh V
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