Semiconductor memory devices and sensors using the same

Details Semiconductor memory devices and sensors using the same Semiconductor memory devices and sensors using the same

2000-05-26

2001-08-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S104000, C365S189011

Reexamination Certificate

active

06282136

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices and sensors using same, in particular, to ROM and RAM of low consuming power and pressure sensors using same.
Currently, integrated circuits for microcomputers and the like, which perform various processing, tend to increase velocity and scale, and have an issue to reduce the consuming current simultaneously with achieving the current tendencies. Accordingly, decreasing its consuming current is required for the semiconductor memory device, which is incorporated with chips such as ROM or RAM. Hereinafter, a conventional example is explained taking ROM as an example of semiconductor device.
FIG. 10
indicates a composition of representative example of ROM using conventional pre-charge system.
The ROM is a semiconductor memory device for storing non-volatile data such as control programs, processing programs, and the like. In accordance with the ROM explained hereinafter, the memory portion is regarded to be composed of memory capacity n×m bits, that is, the memory portion is composed of a matrix having n lines of word line, and m lines of data line.
The ROM indicated in
FIG. 10
is composed of: memory cell array
5
composed of memory cells
50
, wherein data are stored in a non-volatile manner; X decoder, which selects a word line from n word lines
10
in the memory cell array corresponding to an address signal transmitted from address latch
4
to the ROM; m pieces of transistors
90
for pre-charging m data lines
30
; output circuit
7
for reading out the data in the data lines; Y switch
6
composed of m bus-transistors for connecting the output circuit and the data lines; and Y decoder
2
, which selects a line from m Y switch control signal lines corresponding to address signal transmitted from the address latch to the ROM.
Circuit operation of the semiconductor memory device indicated in
FIG. 10
is explained referring to timing chart in
FIG. 11
indicating potential variation in clock and respective signal lines.
When the clock (CLK) is changed from low level (hereinafter, called as L) to high level (hereinafter, called as H), that is, on the rising edge of the clock, the address signal
44
is transmitted to the X decoder
1
and the Y decoder
2
from the address latch
4
, and decoding is started. Decoding the address is completed during the period while the clock is in H, and one of m lines of Y switch control signal lines is selected and changed to H.
Similarly, in accordance with rising of the clock, the pre-charge control signal
9
is changed to L, and the transistors
90
for pre-charging are changed to on. Accordingly, m data lines
30
are pre-charged to power source voltage V
DD
, that is, to H. During the period while the clock is in H, a signal reverse to the clock, that is, L is input to the X decoder
1
. Therefore, any of the word lines does not become H, and the electric charge, which is pre-charged to the data lines, is not withdrawn.
Then, when the clock becomes L, one of the n word lines is selected, and becomes H. At this time, if the memory cell, wherein N channel transistor is formed, is selected, the electric charge of the data line is withdrawn and the data line becomes L, and output signals
8
are output via the output circuit
7
. On the other hand, if the memory cell, wherein N channel transistor is not formed, is selected, the electric charge of the data line is not withdrawn and the data line maintains H, and output signals
8
are output via the output circuit
7
. As explained above, respective of the memory cells
50
of the memory array
5
is programmed by data “1” or “0” during manufacturing process depending on the presence or non-presence of the N channel transistor.
As explained above, in accordance with the pre-charged type ROM, it is indispensable to complete two operations such as “decoding the address” and “pre-charging the data lines” during the clock is in H.
In addition to the above prior art, an example of prior art of semiconductor memory device using improved bit line pre-charging method is disclosed, for instance, in JP-6-119793 (1994)
Prior art, wherein ROM or RAM is used as a part of correcting means for pressure sensor, are disclosed in JP-A-9-113310 (1997), JP-A-10-281912 (1998), but practical circuit composition of these semiconductor memory devices are not described.
Because the conventional semiconductor memory device indicated in
FIG. 10
is composed as described above, all the m lines of the data lines are pre-charged during the clock is in H irrelevant to the actually selected address. This is because, as indicated in the timing chart in
FIG. 11
, the pre-charging and decoding are performed simultaneously in the period when the clock is in H, a data line corresponding to the address can not be selected during the period, and all the data lines must be pre-charged.
As explained above, one of the word lines becomes H during the clock is in L. Therefore, even with the non-selected data lines, in a case when N channel transistor is formed in the memory cell at a crossing point of the above data line and the word line in H , the withdrawn of the electric charge is occurred. The data line must be pre-charged again in the next cycle. As explained above, in accordance with the conventional circuit composition to pre-charge all the data lines, useless consuming current is increased, and as a consequence, a problem to increase consuming current at the memory cell array is occurred.
In order to solve the above problem, for instance, JP-A-6-119792 (1994) discloses a data line selection pre-charging method, wherein only a selected address data line is pre-charged.
The above method utilizes a principle that, because decoding address is completed at relatively first half of the period during the clock is H, the selected data line can be pre-charged after finishing the above operation, that is, decoding and pre-charging can be performed serially during the period when the clock is in H. Accordingly, the data line at the selected address can be pre-charged by composing the circuit in a manner that the drain of the transistor for pre-charging is connected to the data line of the memory cell array via a Y switch. In accordance with this method, significant decrease of the consuming current at the pre-charging can be realized in comparison with the prior art, wherein all the data lines are pre-charged.
However, in accordance with the circuit system disclosed in JP-A-6-119793 (1994), there is a possibility that the transistor for pre-charging becomes on before finishing the decoding, because decoding the address and pre-charging the data line are performed simultaneously from starting-up of the clock. Therefore, practically, a problem is generated that data line of an address which is not selected in the cycle is pre-charged during a period between the time when the transistor for pre-charging becomes on to the time when decoding is finished completely, that is, a period until only a selected path transistor becomes on. In particular, in accordance with the circuit system disclosed in JP-A-6-119793 (1994), because the address of the memory cell are arranged along the word line, the path transistor connected to different data line must be switched on per every cycle even when accessing continuous addresses. Therefore, in accordance with the above reason, the data line at the address selected in the prior cycle is pre-charged again. The output of not only X decoder, but also Y decoder are varied per every cycles, and the consuming current of the decoders is also increased.
SUMMARY OF THE INVENTION
The present invention is achieved in consideration of the above circumstances. One of the main objects of the present invention is to provide a semiconductor memory device, which is capable of decreasing the consuming current at the pre-charging to 1/m (m is the number of data lines), and simultaneously decreasing the consuming current of the decoders, by pre-charging only a data line at the address selected in the cycle.
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