Semiconductor memory devices and methods for sampling data...

Details Semiconductor memory devices and methods for sampling data... Semiconductor memory devices and methods for sampling data...

2001-01-05

2002-04-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S195000, C365S191000, C365S190000, C365S230030, C365S051000

Reexamination Certificate

active

06370068

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-319, filed Jan. 5, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices and, more particularly, to sampling data contained in semiconductor memory devices.
BACKGROUND OF THE INVENTION
The demand for semiconductor memory devices of increasing integration densities is generally increasing. As a result, the size of memory cell arrays may increase in both the word line and bit line dimensions. One potential problem with the increased size of memory cell arrays is that the speed with which data may be read may be different between those memory cells that are closer to the sense amplifiers and those memory cells that are farther away from the sense amplifiers.
A conventional semiconductor memory device typically includes a set of sense amplifiers that amplify and output data from a memory cell array in response to a sense amplifier enable signal. A set of data sampling circuits may also be included that sample respective pairs of output data from the sense amplifiers and pass the sampled data on to other circuitry for further processing in response to a sampling control signal. Typically, the timing of the sampling control signal is adjusted to allow the data sampling circuits to sample the sense amplifier output data that are associated with memory cells that are farthest away from the sense amplifiers. This is to ensure that the data sampling circuits do not attempt to sample the output data from the sense amplifiers too early before the data from memory cells more distant from the sense amplifiers is available. Thus, even though the speed at which data may be read from memory cells that are relatively far away from the sense amplifiers may be relatively slow, the data may nevertheless be sampled and passed on to other circuitry for further processing.
As the integration of semiconductor memory devices increases, however, the difference in the speed at which data is read from memory cells relatively far away from the sense amplifiers and the speed at which data is read from memory cells relatively close to the sense amplifiers may increase. As a result, conventional techniques for sampling data from a memory cell array may be inadequate.
In the same memory cell array block, the difference in speed at which data may be read may be more than 1 ns between memory cells that are relatively far away from the sense amplifiers and memory cells that are relatively close to the sense amplifiers. If the timing of the sampling control signal is adjusted to allow the data sampling circuits to sample the sense amplifier output data that are associated with memory cells that are farthest away from the sense amplifiers, then data associated with memory cells that are relatively close to the sense amplifiers may not be reliably sampled because the data may not be valid when the sampling control signal triggers the data sampling circuits.
For example,
FIG. 1
is a schematic that illustrates a conventional semiconductor memory device that comprises memory cell array blocks
10
-
1
,
10
-
2
, . . . , and
10
-
8
, multiplexers
12
-
1
,
12
-
2
, . . . , and
12
-
9
, sense amplifiers
14
-
1
, . . . ,
14
-
4
, and data sampling circuits
16
-
1
, . . . ,
16
-
4
. In
FIG.1
, multiplexers
12
-
1
,
12
-
2
, . . . , and
12
-
9
are represented as MUX, sense amplifiers
14
-
1
, . . . , and
14
-
4
as SA, and data sampling circuits
16
-
1
, . . . , and
16
-
4
as DS.
In
FIG.1
, pairs of data input output lines IO
11
/B, IO
12
/B, IO
13
/B, and IO
14
/B for a memory cell array block
10
-
1
are arranged on the left and right of the memory cell array block
10
-
1
. Pairs of data input/output line IO
21
/B, IO
22
/B, IO
23
/B, IO
24
/B, IO
31
/B, IO
32
/B, . . . , IO
71
/B, IO
72
/B, IO
81
/B, IO
82
/B, IO
83
/B, and IO
84
/B for the respective memory cell array blocks
10
-
2
, . . . , and
10
-
8
are arranged on the left and right of the corresponding memory cell array block. The pairs of data input/output lines IO
11
/B, IO
12
/B, IO
13
/B, IO
14
/B, IO
21
/B, IO
22
/B, IO
23
/B, IO
24
/B, IO
31
/B, IO
32
/B, . . . , IO
71
/B, IO
72
/B, IO
81
/B, IO
82
/B, IO
83
/B, IO
84
/B for the respective memory cell array blocks
10
-
1
,
10
-
2
, . . . , and
10
-
8
are connected to four pairs of main data input output lines MIO
1
/B, MIO
2
/B, MIO
3
/B, MIO
4
/B. The semiconductor memory device further includes m word select signal lines, which are arranged vertically, for receiving the word select signals WL
1
, WL
2
, and WLm, and n column select signal lines, which are arranged horizontally, for receiving the column select signals CSL
1
, CSL
2
, . . . , and CSLn. The column select signals CSL
1
, CSL
2
, . . . , and CSLn are electrically coupled to corresponding input/output gates IOG.
Operations of the semiconductor memory device of
FIG. 1
are described hereafter. A memory cell may be selected in one of the memory cell array blocks
10
-
1
,
10
-
2
, . . . , and
10
-
8
through activation of one of the word select signals WL
1
, WL
2
, . . . , and WLm and one of the column select signals CSL
1
, CSL
2
, . . . , and CSLn for writing data thereto or reading data therefrom. Multiplexers
12
-
1
,
12
-
2
,
12
-
3
, . . . ,
128
, and
12
-
9
control the input/output of data between the pairs of data input/output lines IO
11
/B, . . . , and IO
14
/B and the pairs of main data input/output lines MIO
1
/B, and MIO
4
/B. For example, if a cell in memory cell array block
10
-
1
is selected, then multiplexers
12
-
1
and
12
-
2
are enabled and data are transmitted between the pairs of data input/output lines IO
11
/B, . . . , and IO
14
/B and the pairs of main data input/output lines MIO
1
/B, . . . , and MIO
4
/B. That is, during a write operation, data are input from the pairs of main data input/output lines MIO
1
/B, . . . , and MIO
4
/B to the pairs of data input/output lines IO
11
/B, . . . , and IO
14
/B. Conversely, during a read operation, data are transmitted from the pairs of data input/output lines IO
11
/B, and IO
14
/B to the pairs of main data input/output lines MIO
1
/B, . . . , and MIO
4
/B.
Although it is not shown, input and output of data is controlled in response to a read and write control signal and corresponding block select signals, which are applied to the multiplexers
12
-
1
,
12
-
2
,
12
-
3
, . . . ,
12
-
8
, and
12
-
9
. The sense amplifiers
14
-
1
, . . . , and
14
-
4
amplify a difference in voltage between data signals on the main data input/output lines MIO
1
/B, . . . , and MIO
4
/B and then output the amplified signals as sense output signal pairs SIO
1
/B, . . . , and SIO
4
/B. The data sampling circuits
16
-
1
, . . . , and
16
-
4
generate data output signals DO
1
, . . . , and DO
4
in response to a sampling control signal FRP.
FIG. 2
illustrates a data sampling circuit of
FIG. 1
in more detail. The data sampling circuit
16
comprises NAND gates NA
1
and NA
2
, an inverter
11
, a PMOS transistor P, and a NMOS transistor N, which are configured as shown. In
FIG. 2
, a sense output signal pair is represented as SIO and SIOB, and an output signal of the data sampling circuit
16
is represented as DO.
Operations of the data sampling circuit
16
of
FIG. 2
are described hereafter. When the sampling control signal FRP is driven to a “low” logic level, both NAND gates NA
1
and NA
2
generate a “high” logic signal at output terminals thereof, regardless of the logic levels of the sense output signals SIO and SIOB. An inverter I
1
generates an output signal at a “low” logic level. Therefore, both the PMOS transistor P and the NMOS transistor N are turned off.
When the sampling control signal FRP is driven to a “high” logic level and the sense output signals SIO and SIOB are at a “high” logic level and “low” logic level, respectively, the NAND gates NA
1
and NA
2
generate output signals at a “low” logic level and a “high” logic lev

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