Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-01-16
2007-01-16
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21209
Reexamination Certificate
active
11243752
ABSTRACT:
Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.
REFERENCES:
patent: 7041572 (2006-05-01), Yang et al.
Dawson Robert
Higgins, Sr. Kelley Kyle
Song Shengnian
Wiseman Joseph William
Booth Richard A.
Ingrassia Fisher & Lorenz P.C.
Spansion LLC
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