Semiconductor memory device with triple metal layer

Details Semiconductor memory device with triple metal layer Semiconductor memory device with triple metal layer

1997-12-08

1999-07-27

Nelms, David

Static information storage and retrieval

Systems using particular element

Semiconductive

257 48, G11C 1134

Patent

active

059301660

ABSTRACT:
A semiconductor memory device formed using a triple metal process to minimize the chip area required to define such a circuit. The semiconductor memory device having a memory cell array and a peripheral circuit for reading and writing data from and into a memory cell. The peripheral circuit includes a circuit layer, a first servicing circuit, a second servicing circuit and a third servicing circuit. The circuit layer, such as a decoder or buffer, defines a peripheral circuit layer area of a semiconductor chip. The first servicing circuit, preferably input/output lines, is defined vertically relative to said peripheral circuit layer area in a first metal layer located in said semiconductor chip. The second servicing circuit, preferably signal bussing lines, is defined vertically relative to said first servicing circuit in a second metal layer located in said semiconductor chip. Finally, the third servicing circuit, such as a power line layer, is defined in a third meal layer vertically relative to said second servicing circuit.

REFERENCES:
patent: 5315130 (1994-05-01), Hively et al.
patent: 5726485 (1998-03-01), Grass

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