Semiconductor memory device with trench capacitor and method for

Details Semiconductor memory device with trench capacitor and method for Semiconductor memory device with trench capacitor and method for

1997-07-22

1998-12-01

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438702, H01L 218242

Patent

active

058438190

ABSTRACT:
A semiconductor memory configuration in a semiconductor substrate includes bit lines, word lines, and memory cells each including one memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode. Each memory capacitor is connected to one of the conducting regions of the transistor. The other of the conducting regions of the transistor is connected to one of the bit lines, and the gate electrode of the transistor is connected to one of the word lines. An insulating field oxide or buried insulating oxide with substantially vertical sidewalls is provided. A trench lies adjacent to the insulating field oxide or buried insulating oxide and adjacent to one of the conducting regions. The capacitors are each disposed in one trench for each memory cell. A first insulating layer covers the inner trench wall surface. A first electrode of the capacitor is disposed perpendicular to the substrate surface on the first insulating layer completely inside the trench. A second insulating layer is disposed on the first electrode. A second electrode is disposed vertically on the second insulating layer in the trench. A contact is connected between the first electrode of the capacitor and one of the conducting regions of the transistor laterally through an opening formed in the first insulating layer on the inner trench wall surface. Methods for producing the semiconductor memory configuration and a memory matrix having at least four of the memory cells, are also provided.

REFERENCES:
patent: 4734384 (1988-03-01), Tsuchiya
patent: 4761385 (1988-08-01), Pfiester
patent: 4786954 (1988-11-01), Morie et al.
patent: 4877750 (1989-10-01), Okumura
patent: 4914740 (1990-04-01), Kenney
patent: 4918500 (1990-04-01), Inuishi
patent: 4921816 (1990-05-01), Ino
patent: 4922313 (1990-05-01), Tsuchiya
patent: 5006910 (1991-04-01), Taguchi
patent: 5016071 (1991-05-01), Kumagai
patent: 5427972 (1995-06-01), Shimizu et al.
patent: 5432113 (1995-07-01), Tani
Half-V.sub.cc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring (Kaga et al.), Transactions on Electron Devices, vol. 35, No. 8, Aug. 1988.
Japanese Patent Abstract No. 61-274357 (Osawa), dated Dec. 4, 1986.

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