Semiconductor memory device with testing of redundant memory cel

Details Semiconductor memory device with testing of redundant memory cel Semiconductor memory device with testing of redundant memory cel

1987-06-09

1989-08-22

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

371 10, 371 21, 365200, G11C 700, G11C 2900

Patent

active

048602604

ABSTRACT:
A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4392211 (1983-07-01), Nakano et al.
patent: 4428068 (1984-01-01), Baba
patent: 4468759 (1984-08-01), Kung et al.
patent: 4549101 (1985-10-01), Sood
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4651304 (1987-03-01), Takata
patent: 4720818 (1988-01-01), Takeguchi

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