Semiconductor memory device with stress circuit and method for s

Static information storage and retrieval – Read/write circuit – Testing

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365194, 365196, G11C 2900

Patent

active

056572824

ABSTRACT:
A semiconductor integrated circuit with a stress circuit and a stress voltage supplying method thereof ensures the reliability of the device. The semiconductor integrated circuit has a stress enable circuit for generating an enable signal during a test operation of the chip and for enabling the test operation, a stress voltage supplying circuit for supplying a first stress voltage and a second stress voltage in response to an output signal of the stress enable circuit during the test operation, and a sensing delay control circuit for receiving the first and second stress voltages and for delaying an operation of the sense amp control circuit during the test operation. During the test operation, the first and second stress voltages are supplied to word lines adjacent to each other in response to the output signal of the stress enable circuit, and a state of a selected memory cell by the word line is sensed in response to an output signal of the sensing delay control circuit.

REFERENCES:
patent: 4527254 (1985-07-01), Ryan et al.
patent: 5119337 (1992-06-01), Shimizu et al.
patent: 5255230 (1993-10-01), Chan et al.
patent: 5258954 (1993-11-01), Furuyama
patent: 5412331 (1995-05-01), Jun et al.

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