Semiconductor memory device with shift redundancy circuits

Details Semiconductor memory device with shift redundancy circuits Semiconductor memory device with shift redundancy circuits

2006-04-11

2006-04-11

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

07027338

ABSTRACT:
A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

REFERENCES:
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5608685 (1997-03-01), Johnson et al.
patent: 5933376 (1999-08-01), Lee
patent: 6021075 (2000-02-01), Ueno
patent: 6765832 (2004-07-01), Ohtani

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