Semiconductor memory device with sense amplifier block

Details Semiconductor memory device with sense amplifier block Semiconductor memory device with sense amplifier block

1999-12-15

2002-02-12

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189110, C365S230030

Reexamination Certificate

active

06347057

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device.
FIG. 9
illustrates the structure of the memory cell peripheral circuits in a semiconductor memory device in the prior art. This semiconductor memory device includes a sense amplifier block sa, a pair of memory cell blocks mc
0
and mc
1
, a pair of word driver blocks wd
1
-
0
and wd
1
-
1
, a pair of decoder blocks dec
1
-
0
and dec
1
-
1
and a control circuit block cnt
1
.
The sense amplifier block sa, to which equalize signals EQ, EQ
0
and EQ
1
, a sense amplifier activating signal SE and transfer signals TG
0
and TG
1
are input, is connected to a bit line pair BL
0
/BL
0
b
and a bit line pair BL
1
/BL
1
b
. The potential levels of the equalize signals EQ, EQ
0
and EQ
1
and the potential level of the sense amplifier activating signal SE swing back and forth between a first source potential VDD and a ground potential VSS, whereas the potential levels of the transfer signals TG
0
and TG
1
swing back and forth between a second source potential VPP and the ground potential VSS.
The sense amplifier block sa is constituted of a sense amplifier unit amp and a sense amplifier control circuit unit acnt.
The sense amplifier unit amp is constituted of PMOS transistors P
0
and P
1
and NMOS transistors N
0
, N
1
, N
00
, N
01
, N
02
, N
03
, N
04
, N
10
, N
11
, N
12
, N
13
and N
14
.
The gate of the PMOS transistor P
0
is connected to a bit line BL, the drain is connected to a bit line BLb and the source is connected to a sense node SP. The gate of the PMOS transistor P
1
is connected to the bit line BLb, the drain is connected to the bit line BL and the source is connected to the sense node SP. The gate of the NMOS transistor N
0
is connected to the bit line BL, the drain is connected to the bit line BLb and the source is connected to a sense node SN. The gate of the NMOS transistor N
1
is connected to the bit line BLb and the drain is connected to the bit line BL and the source is connected to the sense node SN.
On/off control of the NMOS transistor N
00
, whose drain is connected to the bit line BL
0
b
and whose source is connected to the bit line BLb, is implemented by using the transfer signal TG
0
input to the gate. On/off control of the NMOS transistor N
01
, whose drain is connected to the bit line BL
0
and whose source is connected to the bit line BL is implemented by using the transfer signal TG
0
input to the gate.
On/off control of the NMOS transistor N
10
, whose drain is connected to the bit line BL
1
b
and whose source is connected to the bit line BLb is implemented by using the transfer signal TG
1
input to the gate. On/off control of the NMOS transistor N
11
, whose drain is connected to the bit line BL
1
and whose source is connected to the bit line BL is implemented by using the transfer signal TG
1
input to the gate.
On/off control of the NMOS transistor N
02
, whose drain is connected to the bit line BL
0
b
and whose source is connected to a third source potential VBL (=½ VDD) is implemented by using the equalize signal EQ
0
input to the gate. On/off control of the NMOS transistor N
03
, whose drain is connected to the bit line BL
0
and whose source is connected to the third source potential VBL is implemented by using the equalize signal EQ
0
input to the gate. On/off control of the NMOS transistor N
04
, whose drain is connected to the bit line BL
0
b
and whose source is connected to the bit line BL
0
is implemented by using the equalize signal EQ
0
input to the gate.
On/off control of the NMOS transistor N
12
, whose drain is connected to the bit line BL
1
b
and whose source is connected to the source potential VBL is implemented by using the equalize signal EQ
1
input to the gate. On/off control of the NMOS transistor N
13
, whose drain is connected to the bit line BL
1
and whose source is connected to the third source potential VBL is implemented by using the equalize signal EQ
1
input to the gate. On/off control of the NMOS transistor N
14
, whose drain is connected to the bit line BL
1
b
and whose source is connected to the bit line BL
1
, is implemented by using the equalize signal EQ
1
input to the gate.
In response to the sense amplifier activating signal SE, the sense amplifier control circuit unit acnt supplies the first source potential VDD to the sense node SP and supplies the ground potential VSS to the sense node SN. In addition, in response to the equalize signal EQ, it supplies the third sour VBL to the sense node SP and the sense node SN.
In the semiconductor memory device in the prior art illustrated in
FIG. 9
, the equalization (balancing of potentials) for the bit line pair BL
0
/BL
0
b
and the bit line pair BL
1
/BL
1
b
is achieved by supplying third source potential to the bit line pair BL
0
/BL
0
b
and the bit line pair BL
1
/BL
1
b
via the NMOS transistors N
02
, N
03
and N
04
and the NMOS transistors N
12
, N
13
and N
14
respectively.
However, since the gate potentials (=potentials of the equalize signals EQ
0
and EQ
1
) at the NMOS transistors N
02
, N
03
, N
04
, N
12
, N
13
and N
14
during such an equalization operation are at the first source potential VDD, the voltage Vgs between the gates and the sources is at ½ VDD.
When operating the semiconductor memory device in the prior art with the first source potential VDD set at 1.0V~2.0V in order to, for instance, save energy, the voltage Vgs between the gates and the sources at the NMOS transistors N
02
, N
03
, N
04
, N
12
, N
13
and N
14
is set within the range of 0.5V~1.0V, which raises the concern that a sufficient margin relative to the threshold voltage Vt may not be assured. In such a case, limits are set on the currents flowing through the individual NMOS transistors N
02
, N
03
, N
04
, N
12
, N
13
and N
14
, which makes it difficult to equalize the bit line pairs BL
0
/BL
0
b
and BL
1
/BL
1
b
quickly.
Likewise, when equalizing the bit line pair BL/BLb via the NMOS transistors N
00
, N
01
, N
10
and N
11
, too, there is a concern that the length of time required for the equalization may be large since the gate potentials (=potentials of the transfer signals TG
0
and TG
1
) of the individual NMOS transistors N
00
, N
01
, N
10
and N
11
during the equalization operation are set at the first source potential VDD.
In addition, while
FIG. 9
illustrates a semiconductor memory device in the prior art provided with a single sense amplifier block sa, a semiconductor memory device is normally provided with a plurality of sense amplifier blocks and consequently, a plurality of memory cell blocks and a plurality of word driver blocks in correspondence. Furthermore, each sense amplifier block is provided with a great number of sense amplifiers. When the number of sense amplifiers increases in this manner, parasitic capacitance and parasitic resistance in the lines through which the equalize signals EQ
0
and EQ
1
are provided increase, which results in a delay occurring when the potential levels of the equalize signals EQ
0
and EQ
1
shift.
In the semiconductor memory device in the prior art illustrated in
FIG. 9
, when reading out data stored in a cell capacitor C
00
, for instance, it is necessary to shift the potential at a word line WL
00
to the second source potential VPP after the potential of the equalize signal EQ
0
shifts to the ground potential VSS and the bit line pair BL
0
/BL
0
b
are completely cut off from the third source potential VBL to ensure that a read error does not occur due to the electrical charge discharged from the cell capacitor C
00
discharged to the third source potential VBL via the NMOS transistors N
02
and N
03
. However, the delay occurring in the shift of the potential levels of the equalize signals EQ
0
and EQ
1
described above necessitates a delay in the timing with which the potential level at the word line shifts and, consequently, the access speed of the semiconductor memory device is lowered.
SUMMARY OF THE INVENTION
An object of the present invention, w

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