Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-11-21
1996-06-04
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
36518907, 365210, G11C 700
Patent
active
055239749
ABSTRACT:
A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.
REFERENCES:
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4783781 (1988-11-01), Awaga
patent: 5128944 (1992-07-01), Flaherty et al.
patent: 5357458 (1994-10-01), Yu et al.
patent: 5381370 (1995-01-01), Lacey et al.
Hirano Hiroshige
Moriwaki Nobuyuki
Mukunoki Toshio
Nakakuma Tetsuji
Nakane George
Dinh Son
Matsushita Electric - Industrial Co., Ltd.
Nelms David C.
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