Semiconductor memory device with redundancy structure

Details Semiconductor memory device with redundancy structure Semiconductor memory device with redundancy structure

1995-06-07

1997-03-11

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 365 96, G11C 700

Patent

active

056108656

ABSTRACT:
A semiconductor memory device with redundancy structure having a normal memory cell array having a plurality of normal memory cells arranged in row and column directions and a redundant memory cell array having a plurality of redundant memory cells, includes a redundant column selecting circuit for comparing an externally applied column address signal and a programmed defective column address signal to generate a redundant column selection signal. The redundant column selecting circuit has a programming circuit portion for producing the programmed defective column address signal by programming a defective column address corresponding to a defective column. A decoding circuit is provided for decoding the column address signals and producing a column decoding signal; and a normal column selecting circuit for receiving the column decoding signal and producing a normal column selection signal, and which has a disabling circuit for disabling the normal column selecting circuit and enabling the redundant column selecting circuit when the defective column address is applied. When a redundant column is substituted for a defective column with the present invention, since the normal column selection circuit can be operated independently of output signals of fusing boxes provided in a redundant column selection circuit, mal-operation of column and redundant selection circuits can be prevented and the gate passing time of a signal is shortened so as to achieve a high speed operation of the circuits.

REFERENCES:
patent: 5383156 (1995-01-01), Komatsu
patent: 5426607 (1995-06-01), Ishibashi

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