Semiconductor memory device with reduced sensing noise and...

Details Semiconductor memory device with reduced sensing noise and... Semiconductor memory device with reduced sensing noise and...

2000-04-20

2001-07-10

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S230030, C365S230060

Reexamination Certificate

active

06259642

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having reduced sensing noise and sensing current by decreasing the number of memory cells activated by a word line.
2. Description of the Related Art
FIG. 1
shows a typical configuration of a conventional semiconductor memory device. Referring to
FIG. 1
, memory cells in a memory cell array
10
are arranged in a matrix form, and sub-word lines
12
and bit lines
14
for selecting memory cells to be accessed are arranged in column and row directions, respectively. A memory cell (not shown) is disposed at an intersection of a sub-word line
12
and a bit line
14
.
A sub-word line driver
16
disposed below the memory cell array
10
activates one of the sub-word lines
12
in response to a pre-word line signal PW provided from a pre-word line decoder (not shown). Sense amplifiers (S/As)
18
a
and
18
b
disposed at the sides of the memory cell array
10
are connected to the bit lines
14
to read data from memory cells selected by the sub-word line and the bit lines
14
. The sub-word line driver
16
drives one of the sub-word lines
12
in response to the pre-word line signal PW which is decoded by the pre-word line decoder (not shown) and a signal PX made from a row address. One of the bit lines
14
connected to the sub-word line
12
driven by the sub-word line driver
16
is selected by a column address. Memory capacity of a semiconductor memory device as shown in
FIG. 1
may be increased by extending the memory cell array
10
in the row or column direction.
FIG. 2
shows a configuration of a semiconductor memory device in which a memory cell array is extended in the row direction. Referring to
FIG. 2
, memory cell groups
20
a
and
20
b
each having a size of n×n memory cells are arranged in the row direction. Sub-word line drivers
26
a
and
26
b
are respectively disposed below the memory cell groups
20
a
and
20
b
. Sense amplifiers
28
a
,
28
b
and
28
c
are disposed at the sides of the memory cell groups.
In response to a pre-word line signal PW, a signal PX and group select signals RAi/RAiB which are obtained by decoding a row address, one of the sub-word line drivers
26
a
and
26
b
drives one of the sub-word lines
22
in a memory cell group. One of bit lines
24
connected to the driven sub-word line
22
is selected by a column address.
As compared with the memory cell array of
FIG. 1
, the memory cell array of
FIG. 2
has a disadvantage in that an area required for decoding the row address increases. To overcome this problem, a memory cell array as shown in
FIG. 3
is employed.
FIG. 3
shows a configuration of a semiconductor memory device in which a memory cell array is extended in a column direction. Referring to
FIG. 3
, memory cell groups
30
a
and
30
b
each having a size of n×n memory cells are arranged in the column direction. A sub-word line driver
36
is disposed below the memory cell group
30
a
. Sense amplifiers
38
a
and
38
b
are disposed at the sides of the memory cell groups
30
a
and
30
b
. Sub-word lines
32
are commonly used in the memory cell groups
30
a
and
30
b
and driven by the sub-word line driver
36
. Each sense amplifier
38
a
is controlled by a sense amplifier control circuit
39
.
The sub-word line driver
36
drives one of the sub-word lines
32
in response to a pre-word line signal PW and a signal PX. One of bit lines
34
connected to the driven sub-word line
32
is selected by a column address and group select signals RAi and RAiB. In
FIG. 3
, the group select signals RAi and RAiB are used for selecting the bit line
34
, not the sub-word line
32
.
Compared with the device of
FIG. 2
, the device of
FIG. 3
does not increase the area required for decoding the row address but has a disadvantage in that the number of memory cells to be sensed increases. In the memory cell array shown in
FIG. 3
, when one of the sub-word lines
32
is selected by the pre-word line signal PW and the signal PX,
2
n
bit lines
34
connected to the selected sub-word line
32
are activated. At this time, the group select signals RAi and RAiB are applied to a column decoder (not shown) so that either a bit line
34
in the upper memory cell group
30
b
or a bit line
34
in the lower memory cell group
30
a
is selected.
When the sub-word line
32
is activated and data in memory cells are transmitted to the
2
n
bit lines
34
,
2
n
sense amplifiers
38
a
and
38
b
perform sensing operation with respect to the data in the
2
n
bit lines in response to a signal for driving the sense amplifiers
38
a
and
38
b
. In this case, while a bit line
34
in the upper memory cell group
30
b
is selected by a column address and the group select signal RAiB, no operation such as read or write is performed in the memory cells of the lower memory cell group
30
a
. However, data in the memory cells in the lower memory cell group
30
a
are still restored by the sense amplifiers
38
a
and
38
b
because the sub-word line
32
connected to the
2
n
bit lines of the upper and low memory cell groups
36
b
and
36
a
is selected. As a result, unnecessary sensing operation is performed in the lower memory cell group
30
a
. This causes sensing noise and sensing current to increase. In a like manner, such unnecessary sensing operation also occurs in the upper memory cell group
30
b
, when the lower memory cell group
30
a
is selected by the group select signal RAi.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device having reduced sensing noise and sensing current by preventing unnecessary sensing operation from occurring in a memory cell group which is not selected.
To achieve the above and other objects of the present invention, there is provided a semiconductor memory device including a plurality of memory cell groups obtained by segmenting a memory cell array in a column direction, each memory cell group being selected by a group selection signal, a plurality of sub-word line drivers for selectively activating a sub-word line of a memory cell group activated in response to the group selection signal, and a plurality of controllers for controlling sense amplifiers connected to bit lines of the plurality of memory cell groups, a controller providing driving voltages to a corresponding sense amplifier connected to the memory cell group activated in response to the group selections signal.


REFERENCES:
patent: 5416748 (1995-05-01), Fujita
patent: 6094381 (2000-07-01), Isa
patent: 6111808 (2000-08-01), Khang et al.
patent: 6118723 (2000-09-01), Agata et al.

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