Semiconductor memory device with reduced package test time

Details Semiconductor memory device with reduced package test time Semiconductor memory device with reduced package test time

2007-07-24

2007-07-24

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

10331728

ABSTRACT:
A semiconductor memory device capable of performing a package test with bandwidth other than the default bandwidth without any wiring modification with respect to package option pads reduces package test time. The present invention implements the other package options based upon the wire bonding with an internal option. According to the operation mode, buffer control signals are used to control a VDD or VSS applied to the package option pads via the wire bonding. Buffer control signal are generated using a mode register reset. The buffer receiving the buffer control signal outputs the signal corresponding to the wiring state of the package option pad, blocks the signal path from the package option pads, and outputs a signal corresponding to a package option other than the default package option.

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patent: 6229726 (2001-05-01), Wang et al.
patent: 6976200 (2005-12-01), Ohbayashi
patent: 7076705 (2006-07-01), Ohbayashi
patent: 06069425 (1994-03-01), None
patent: 2000-150564 (2000-05-01), None
patent: 2002-35457 (2004-06-01), None

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