Semiconductor memory device with reduced data bus line load

Details Semiconductor memory device with reduced data bus line load Semiconductor memory device with reduced data bus line load

1997-07-08

1999-05-25

Mai, Son

Static information storage and retrieval

Read/write circuit

Precharge

36523003, G11C 700

Patent

active

059075163

ABSTRACT:
A semiconductor memory device having a plurality of memory blocks for storing data, and a plurality of sense amplifiers for sensing the data stored in the plurality of memory blocks. The semiconductor memory device comprises data bus lines for transferring the data sensed by the plurality of sense amplifiers. The data bus lines are divided into first and second parts. The semiconductor memory device further comprises a data bus line load reduction circuit for selecting one of the divided first and second data bus line parts in response to first and second data bus line control signals. The selected data bus line part inputs the data from one of the plurality of memory blocks selected in response to a memory block address. The other data bus line part, not selected, has a minimized load. The first and second data bus line control signals are produced in response to a most significant bit of the memory block address.

REFERENCES:
patent: 4799197 (1989-01-01), Kodama
patent: 4991142 (1991-02-01), Wang
patent: 5016224 (1991-05-01), Tanaka et al.
patent: 5243574 (1993-09-01), Ikeda
patent: 5444305 (1995-08-01), Matsui

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