Semiconductor memory device with reduced current consumption dur

Details Semiconductor memory device with reduced current consumption dur Semiconductor memory device with reduced current consumption dur

1996-09-05

1998-01-13

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

36518902, 365227, 36523004, G11C 700

Patent

active

057086150

ABSTRACT:
A semiconductor memory device with low current consumption is disclosed. A bit line selecting circuit (3) establishes electrical connection between a bit line (BL) selected during a read period and a node (N2) in response to bit line connection/selection signals (SB0 to SB4). A charge-up circuit (7) includes PMOS transistors (Q29, Q30). The PMOS transistor (Q29) has a source connected to a power supply (V.sub.DD), a drain connected to a drain of a transistor (Q10) of the bit line selecting circuit (3), and a gate receiving a read control signal (SC). The PMOS transistor (Q30) has a source connected to the power supply (V.sub.DD), a drain connected to the drain of the transistor (Q10) of the bit line selecting circuit (3), and a gate fixed at a ground level.

REFERENCES:
patent: 5040148 (1991-08-01), Nakai et al.
patent: 5331600 (1994-07-01), Higuchi

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