Semiconductor memory device with precharge voltage correction ci

Details Semiconductor memory device with precharge voltage correction ci Semiconductor memory device with precharge voltage correction ci

1999-11-03

2000-11-14

Phan, Trong

Static information storage and retrieval

Read/write circuit

Precharge

G11C 700

Patent

active

061479160

ABSTRACT:
A semiconductor memory device, such as a DRAM, includes a memory cell array and pairs of bit lines connected to the memory cells in the array. A precharge circuit is connected the bit line pairs and selectively provides the bit line pairs with a reference power supply voltage when the memory cells are being accessed and a precharge voltage when the memory cells are not being accessed. A correction circuit adjusts the precharge voltage in accordance with a difference between the precharge voltage and the reference power supply voltage so that the precharge voltage becomes substantially equal to the reference power supply voltage. A retention mode determination circuit detects when the memory device is in a retention mode (powered down state) and prevents access to the memory cells at this time.

REFERENCES:
patent: 4404660 (1983-09-01), Menachem
patent: 5379265 (1995-01-01), Yamada et al.
patent: 5434822 (1995-07-01), Deleganes et al.
patent: 5604704 (1997-02-01), Atsumo
patent: 5636169 (1997-06-01), Oh
patent: 5689470 (1997-11-01), Inoue
patent: 5892722 (1999-04-01), Jang et al.

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