Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2008-05-13
2008-05-13
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S193000, C365S233100
Reexamination Certificate
active
07372745
ABSTRACT:
A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal. A control circuit separately generates the data control signal and the data strobe control signal. A data latch circuit latches the data signal from the data signal input circuit in response to the data strobe signal from the data strobe signal input circuit. A memory cell array has a plurality of memory cells arranged in a matrix. The latched data signal is stored in a selected one of the plurality of memory cells through the data buffer, an amplifier circuit configured to amplify a data signal read out from the selected memory cell; and an output circuit configured to output the amplified data signal.
REFERENCES:
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 6680866 (2004-01-01), Kajimoto
patent: 2000-156083 (2000-06-01), None
patent: 3317912 (2002-06-01), None
patent: 2003-59267 (2003-02-01), None
patent: 2003-272379 (2003-09-01), None
Dinh Son
Elpida Memory Inc.
McGinn IP Law Group PLLC
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