Semiconductor memory device with IO compression test mode

Details Semiconductor memory device with IO compression test mode Semiconductor memory device with IO compression test mode

2000-09-08

2001-10-09

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S063000, C365S189020

Reexamination Certificate

active

06301169

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having an IO compression test mode.
2. Description of the Background Art
FIG. 15
is a diagram schematically showing an entire configuration of a conventional semiconductor memory device. The semiconductor memory device MD in
FIG. 15
includes: memory arrays MA
0
-MA
3
respectively disposed for quartered regions of a chip; and row decoders RD
0
-RD
3
provided corresponding to respective memory arrays MA
0
-MA
3
for driving addressed rows in corresponding memory arrays MA
0
-MA
3
to a selected state. Each of memory arrays MA
0
-MA
3
has a storage capacity, for example, of 16M bits, and semiconductor memory device MD has a storage capacity of 64M bits, for example.
Column related circuit blocks CP
0
-CP
3
are provided corresponding to memory arrays MA
0
-MA
3
, respectively. Each of column related circuit blocks CP
0
-CP
3
includes: a column decoder selecting an addressed column, a preamplifier for amplifying data in a memory cell selected by the column decoder; and a write driver for writing data to the memory cell selected by the column decoder.
In a central region between memory arrays MA
0
, MA
2
and memory arrays MA
1
, MA
3
, an internal data bus DBB is disposed common to memory arrays MA
0
-MA
3
. Internal data bus DBB has a bus width, for example, of 16 bits, and a prescribed number of data lines are used according to the pin arrangement (e.g., ×4, ×8 and ×16) of semiconductor memory device MED.
In the central region between memory arrays MA
0
and MA
1
, a peripheral pad group PPG is disposed to receive an address signal and a control signal. In the central region between memory arrays MA
2
and MA
3
, a DQ pad group DPG is disposed for sending and receiving data to and from internal data bus DBB. Peripheral pad group PPG and DQ pad group DPG include buffering circuits provided corresponding to the pads.
In this semiconductor memory device MD, one memory array is selected in operation for data access. This is because semiconductor memory device MD takes a bank configuration, and each of memory arrays MA
0
-MA
3
can be utilized as a bank.
FIG. 16
is a diagram schematically showing a configuration of memory array MAi (i=0-3). Memory array MAi in
FIG. 16
is divided into memory cell blocks MB
00
-MBmn arranged in rows and columns. Memory cell blocks MB
00
-MBmn each have, for example, a storage capacity of 128K bits, and they are placed in eight rows and eight columns.
A sub word driver is disposed between memory cell blocks aligned in a row direction, for driving a word line of a corresponding memory cell block to a selected state. Sub word driver bands SWD
1
-SWDn having the sub word drivers disposed therein extend within the memory array in a column direction. Sub word driver bands SWD
0
and SWDn+1 are placed outside the memory cell blocks.
In memory array MA, a hierarchical word line configuration is utilized. More specifically, a main word line is placed commonly to memory cell blocks aligned in a row direction. In the memory cell blocks, sub word lines are placed corresponding to respective rows of memory cells. Memory cells in each row in the memory cell block are connected to a corresponding sub word line. A sub word driver included in a sub word driver band drives a corresponding sub word line to a selected state according to a signal on the main word line and a predecode signal from a row decoder. This predecode signal is utilized for selecting one of a plurality of sub word lines provided corresponding to a single main word line.
Sense amplifier bands SAB
1
-SABm are placed between the memory cell blocks aligned in a column direction, and sense amplifier bands SAB
0
and SABm+1 are placed at both sides of the memory array. Each of sense amplifier bands SAB
0
-SABm+1 includes: a sense amplifier circuit for sensing, amplifying and latching data of a memory cell in a corresponding column of memory cell blocks; an IO gate (column select gate) for connecting a corresponding column to an internal data transmission line according to a column select signal from the column decoder; and a bit line precharge/equalize circuit for precharging/equalizing a bit line. Each of sense amplifier bands SAB
1
-SABm is shared by memory cell blocks adjacent to each other in the column direction.
In memory array MA, memory cells of 16 bits are selected at one time, and the memory cells of 16 bits are coupled to corresponding preamplifier + write driver blocks via the internal data transmission lines (not shown).
FIG. 17
is a diagram schematically showing an arrangement of internal data transmission lines in the memory array shown in FIG.
16
. In
FIG. 17
, memory cell blocks MB
40
-MB
77
arranged in four rows and eight columns are shown. Such an array configuration as shown in
FIG. 17
is disposed repeatedly in both row and column directions.
In each of sense amplifier bands SAB
4
-SAB
8
, local IO line pairs LIOP are disposed, each pair being placed corresponding to a prescribed number of memory cell blocks. In the arrangement shown in
FIG. 17
, in each of sense amplifier bands SAB
4
-SAB
8
, two local IO line pairs LIOP are disposed for four memory cell blocks adjacent to each other in the row direction. Each of memory cell blocks MB
40
-MB
77
simultaneously sends and receives data to and from the local IO line pairs included in the sense amplifier bands at both sides thereof in the column direction. In the memory cell blocks along which local IO line pairs LIOP extend, memory cells of 4 bits are selected at a time.
For sub wofrd driver bands SWD
0
-SWD
8
, global IO line pairs GIOP
0
-GIOP
7
are disposed in every other sub word driver bands SWD
1
, SWD
3
, SWD
5
and SWD
7
in a unit of two global IO line pairs. Local IO line pair LIOP and global IO line pair GIOP (GIOP
0
-GIOP
7
) are coupled to each other via a block select gate BSG. Block select gate BSG is driven to a selected state when memory cell blocks aligned in a row direction are selected, and couples corresponding local IO line pair LIOP and global IO line pair GIOP.
A column decoder CD is provided common to the memory cell blocks. Column decoder CD drives one column select line for four memory cell blocks adjacent to each other in the row direction, to a selected state according to a column address signal. This column select line can select memory cells of 4 bits simultaneously. Column decoder CD drives two column select lines to a selected state, and thus, memory cells of 8 bits in total are coupled to global IO line pairs GIOP
0
-GIOP
7
.
Global IO line pairs GIOP
0
-GIOP
7
are coupled to a preamplifier + write driver block PW. In this preamplifier + write driver block PW, two global IO line pairs out of 8 bits of global IO line pairs GIOP
0
-GIOP
7
are coupled to internal data bus DBB. In the case of a ×4-bit configuration, this internal data bus DBB also sends and receives data of 2 bits to and fifom another preamplifier + write driver block not shown, provided for other memory blocks.
FIG. 18
is a diagram schematically showing a configuration of a portion related to one memory cell block shown in FIG.
17
. Referning to
FIG. 18
, in each memory cell block, memory cells MC's are arranged in rows and columns, and a sub word line WL is disposed corresponding to each row of the memory cells. In
FIG. 18
, sub word lines WL (m−7)-WL (m+6) are shown representatively. A bit line pair is placed corresponding to each column of the memory cells. In
FIG. 18
, bit line pairs BL (n−1), ZBL (n−1)-WL (n+3), ZBL (n+3) are shown representatively. In the memory cell block, memory cells of 2 bits are coupled to the same bit line via one contact hole. Memory cells MC's aligned in the row direction are coupled either to a true bit line BL or to a complementary bit line ZBL.
Column select gates CSG's are placed alternately at both

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