Semiconductor memory device with improved substrate arrangement

Details Semiconductor memory device with improved substrate arrangement Semiconductor memory device with improved substrate arrangement

1995-05-02

1998-09-08

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

365193, G11C 700

Patent

active

058055134

ABSTRACT:
A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

REFERENCES:
patent: 4751679 (1988-06-01), Dehganpour
patent: 5016220 (1991-05-01), Yamagata
patent: 5245577 (1993-09-01), Duesman
patent: 5249155 (1993-09-01), Arimoto
patent: 5400290 (1995-03-01), Suma

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