Semiconductor memory device with improved precharge timing

Details Semiconductor memory device with improved precharge timing Semiconductor memory device with improved precharge timing

2006-07-04

2006-07-04

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S203000

Reexamination Certificate

active

07072228

ABSTRACT:
A memory cell array has a plurality of memory cells arranged in row and columns, and bit lines and word lines connected to the memory cells. A command buffer circuit receives at least an active signal to activate one of the rows, and a clock signal, and generates an internal precharge signal to precharge the bit lines based on the active signal.

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