Semiconductor memory device with improved output to differential

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365190, 365194, 365203, 365204, 36523008, 3652335, 307473, G11C 700

Patent

active

050439448

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of memory cells, each of the cells being capable of storing a data and being selected by an address; a pair of data lines to which a pair of complementary data from a selected memory cell are imputted; an equalizer for short-circuiting and equalizing the pair of data lines when an equalizing signal is applied; an output circuit for outputting a single signal corresponding to the pair of complementary data from the pair of data lines; a pair of latch circuits provided between the output circuit and the equalizer for the pair of data lines, the pair of latch circuits holding the pair of complementary data; a pair of output buffer circuit provided between the pair of latch circuits and the equalizer for the pair of data lines, the pair of output buffer circuits capable of taking a low impedance state wherein the potentials per se of the pair of data lines are outputted, and a high impedance state wherein the potential change of the pair of data lines is not transmitted to the output side of the pair of output buffer circuits; and a controller for generating a first control signal which makes the pair of output buffer circuits to enter the high impedance state before the equalizing signal is applied to the equalizer and a second control signal which makes the pair of output buffer circuits to enter the low impedance state after the equalizing signal is turned off.

REFERENCES:
patent: 4573147 (1986-02-01), Aoyama et al.
patent: 4603403 (1986-07-01), Toda
patent: 4620298 (1986-10-01), Ozawa
patent: 4817054 (1989-03-01), Banerjee et al.
patent: 4843595 (1989-06-01), Suzuki
patent: 4881203 (1989-11-01), Watanabe et al.

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