Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-03-22
2004-05-25
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
26, 26
Reexamination Certificate
active
06741505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device that compares a potential of a dummy bit line with a reference voltage, and generates various kinds of timing signals.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. For example, along with an increase in the memory capacity of a semiconductor memory device like an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory), the operation speed has been increased and the power consumption of this semiconductor memory device has been reduced. Further, there has been a demand for the provision of semiconductor memory devices that can achieve higher-speed operation regardless of variations in semiconductor manufacturing processes and manufacturing lines.
In a DRAM, various kinds of timing signals are generated by a timing signal generating circuit that is provided within the DRAM. Conventionally, for example, a sense amplifier enabling signal has been generated by adjusting a timing, based on an insertion of a delay circuit that gives a suitable delay time to the timing signal generating circuit. This adjustment has been carried out to generate a sufficient difference in voltage amplitudes in bit lines or data buses, during a period from when a word line signal is activated until when a sense amplifier starting signal is activated. This has been done regardless of variations in the memory cell process.
The delay circuit (which may be formed by a plurality of inverters connected in cascade) provided in the timing signal generating circuit outputs the sense amplifier enabling signal of the sense amplifier after a delay time since the selection of a word line. Nevertheless, in reading the same data that are stored in the memory cells, voltages (voltage amplitudes) between the bit lines are different from each other. This is because of differences in parasitic capacitance at locations of the memory cells in a memory cell array, or variations in semiconductor manufacturing processes and manufacturing lines. Further, an input offset voltage of the sense amplifier also varies depending on the variations in semiconductor manufacturing processes and manufacturing lines, or the temperatures of the environments in which they are used. Therefore, when it is possible to obtain only the input offset that is below the operation margin of the sense amplifier, the sense amplifier cannot correctly read the data.
The prior art and the problems associated with the prior art will be described in detail later with reference to accompanying drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that can substantially improve the operation margin and can further increase the operation speed regardless of variations in semiconductor manufacturing processes and manufacturing lines.
According to the present invention, there is provided a semiconductor memory device comprising a dummy bit line having a load equal to a load of a bit line; a reference voltage generating circuit generating a reference voltage; a comparator circuit comparing a potential of the dummy bit line with the reference voltage; and a timing signal generating circuit generating various kinds of timing signals based on an output of the comparator circuit, wherein the semiconductor memory device simultaneously selects a plurality of dummy memory cells and connects the selected dummy memory cells to the dummy bit line, and adjusts the potential of the dummy bit line.
Further, according to the present invention, there is also provided a semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each provided at an intersection point of the word line and the bit line; a word driver driving a predetermined word line in the memory cell array according to an address signal; a dummy bit line simulating the bit line; a reference voltage generating circuit generating a reference voltage; a comparator circuit comparing a potential of the dummy bit line with the reference voltage; a timing signal generating circuit generating various kinds of timing signals based on an output of the comparator circuit; and a plurality of dummy memory cells being simultaneously connectable to the dummy bit line.
The dummy memory cells may be a plurality of reading dummy memory cells that are driven by a dummy word line. A plurality of load dummy memory cells may be connected to the dummy word line. A plurality of load dummy memory cells may be connected to the dummy bit line. The number of the dummy memory cells that are connected simultaneously may be adjusted in a layout process.
The semiconductor memory device may further comprise a switching circuit controlling the number of dummy memory cells that are connected simultaneously. The semiconductor memory device may further comprise a dummy memory cell selection signal generating circuit generating a dummy memory cell selection signal according to a dummy memory cell selection control signal; and a dummy memory cell selecting circuit selecting a plurality of dummy memory cells that are connected simultaneously according to the dummy memory cell selection signal. The dummy memory cell selecting circuit may be formed as a switch having a reset function.
The comparator circuit may be a current-mirror type differential amplifier. The semiconductor memory device may further comprise a comparator circuit output resetting circuit that resets an output of the comparator circuit when the comparator is inactive. The semiconductor memory device may further comprise a bit-line equalizing circuit that resets potentials of the bit lines and the dummy bit line to a predetermined voltage, wherein the comparator circuit becomes inactive when the bit-line equalizing circuit is active, and the comparator circuit becomes active when the bit-line equalizing circuit is inactive.
The semiconductor memory device may further comprise a dummy load capacitance provided in a wiring route from the bit-line equalizing circuit to the comparator circuit. The semiconductor memory device may further comprise a data bus equalizing circuit resetting potentials of data buses or dummy data buses to a predetermined voltage, wherein the comparator circuit becomes inactive when the data bus equalizing circuit is active, and the comparator circuit becomes active when the data bus equalizing circuit is inactive.
The semiconductor memory device may further comprise a sense amplifier reading a data of a memory cell that is connected to a predetermined word line; and an output latch circuit latching an output of the sense amplifier. The semiconductor memory device may further comprise a dummy sense amplifier provided in a wiring route from the bit-line equalizing circuit to the comparator circuit, and simulating a load of the sense amplifier; and a dummy output latch circuit simulating a load of the output latch circuit. The semiconductor memory device may further comprise a column switch selecting a predetermined bit line from among a plurality of bit lines, and connects the selected bit line to the sense amplifier, wherein the column switch makes the dummy bit line simulate the loads of a plurality of bit lines to be selected.
REFERENCES:
patent: 4751681 (1988-06-01), Hashimoto
patent: 5889718 (1999-03-01), Kitamoto et al.
patent: 07-093972 (1995-04-01), None
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nelms David
Nguyen Thinh T
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